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/linux/drivers/phy/broadcom/
H A Dphy-brcm-usb-init-synopsys.c1 // SPDX-License-Identifier: GPL-2.0
13 #include "phy-brcm-usb-init.h"
36 /* Register definitions for the USB CTRL block */
110 void __iomem *usb_mdio = params->regs[BRCM_REGS_USB_MDIO]; in usb_mdio_write_7211b0()
112 addr &= 0x1f; /* 5-bit address */ in usb_mdio_write_7211b0()
128 void __iomem *usb_mdio = params->regs[BRCM_REGS_USB_MDIO]; in usb_mdio_read_7211b0()
130 addr &= 0x1f; /* 5-bit address */ in usb_mdio_read_7211b0()
155 void __iomem *ctrl = params->regs[BRCM_REGS_CTRL]; in xhci_soft_reset() local
156 void __iomem *xhci_gbl = params->regs[BRCM_REGS_XHCI_GBL]; in xhci_soft_reset()
160 USB_CTRL_UNSET(ctrl, USB_PM, XHC_SOFT_RESETB); in xhci_soft_reset()
[all …]
/linux/drivers/net/mdio/
H A Dmdio-bitbang.c1 // SPDX-License-Identifier: GPL-2.0
18 #include <linux/mdio-bitbang.h>
44 static void mdiobb_send_bit(struct mdiobb_ctrl *ctrl, int val) in mdiobb_send_bit() argument
46 const struct mdiobb_ops *ops = ctrl->ops; in mdiobb_send_bit()
48 ops->set_mdio_data(ctrl, val); in mdiobb_send_bit()
50 ops->set_mdc(ctrl, 1); in mdiobb_send_bit()
52 ops->set_mdc(ctrl, 0); in mdiobb_send_bit()
56 static int mdiobb_get_bit(struct mdiobb_ctrl *ctrl) in mdiobb_get_bit() argument
58 const struct mdiobb_ops *ops = ctrl->ops; in mdiobb_get_bit()
61 ops->set_mdc(ctrl, 1); in mdiobb_get_bit()
[all …]
/linux/drivers/nvme/target/
H A Dpr.c1 // SPDX-License-Identifier: GPL-2.0
30 struct nvmet_pr_registrant *reg; in nvmet_pr_find_registrant() local
32 list_for_each_entry_rcu(reg, &pr->registrant_list, entry) { in nvmet_pr_find_registrant()
33 if (uuid_equal(&reg->hostid, hostid)) in nvmet_pr_find_registrant()
34 return reg; in nvmet_pr_find_registrant()
41 u32 nsid = le32_to_cpu(req->cmd->common.nsid); in nvmet_set_feat_resv_notif_mask()
42 struct nvmet_ctrl *ctrl = req->sq->ctrl; in nvmet_set_feat_resv_notif_mask() local
48 req->error_loc = offsetof(struct nvme_common_command, cdw11); in nvmet_set_feat_resv_notif_mask()
56 if (!req->ns->pr.enable) in nvmet_set_feat_resv_notif_mask()
59 WRITE_ONCE(req->ns->pr.notify_mask, mask); in nvmet_set_feat_resv_notif_mask()
[all …]
/linux/drivers/soundwire/
H A Dqcom.c1 // SPDX-License-Identifier: GPL-2.0
107 #define SWRM_DPn_PORT_CTRL_BANK(offset, n, m) (offset + 0x100 * (n - 1) + 0x40 * m)
108 #define SWRM_DPn_PORT_CTRL_2_BANK(offset, n, m) (offset + 0x100 * (n - 1) + 0x40 * m)
109 #define SWRM_DPn_BLOCK_CTRL_1(offset, n) (offset + 0x100 * (n - 1))
110 #define SWRM_DPn_BLOCK_CTRL2_BANK(offset, n, m) (offset + 0x100 * (n - 1) + 0x40 * m)
111 #define SWRM_DPn_PORT_HCTRL_BANK(offset, n, m) (offset + 0x100 * (n - 1) + 0x40 * m)
112 #define SWRM_DPn_BLOCK_CTRL3_BANK(offset, n, m) (offset + 0x100 * (n - 1) + 0x40 * m)
113 #define SWRM_DPn_SAMPLECTRL2_BANK(offset, n, m) (offset + 0x100 * (n - 1) + 0x40 * m)
130 #define SWRM_REG_VAL_PACK(data, dev, id, reg) \ argument
131 ((reg) | ((id) << 16) | ((dev) << 20) | ((data) << 24))
[all …]
/linux/arch/arm64/kernel/
H A Dhw_breakpoint.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * HW_breakpoint: a unified kernel/user-space hardware breakpoint facility,
10 #define pr_fmt(fmt) "hw-breakpoint: " fmt
23 #include <asm/debug-monitors.h>
37 /* Currently stepping a per-CPU kernel breakpoint. */
61 #define READ_WB_REG_CASE(OFF, N, REG, VAL) \ argument
63 AARCH64_DBG_READ(N, REG, VAL); \
66 #define WRITE_WB_REG_CASE(OFF, N, REG, VAL) \ argument
68 AARCH64_DBG_WRITE(N, REG, VAL); \
71 #define GEN_READ_WB_REG_CASES(OFF, REG, VAL) \ argument
[all …]
/linux/drivers/gpio/
H A Dgpio-realtek-otto.c1 // SPDX-License-Identifier: GPL-2.0-only
42 * struct realtek_gpio_ctrl - Realtek Otto GPIO driver data
46 * @cpumask_base: Base address of the per-CPU interrupt mask registers
51 * @bank_read: Read a bank setting as a single 32-bit value
52 * @bank_write: Write a bank setting as a single 32-bit value
55 * The DIR, DATA, and ISR registers consist of four 8-bit port values, packed
56 * into a single 32-bit register. Use @bank_read (@bank_write) to get (assign)
57 * a value from (to) these registers. The IMR register consists of four 16-bit
58 * port values, packed into two 32-bit registers. Use @imr_line_pos to get the
59 * bit shift of the 2-bit field for a line's IMR settings. Shifts larger than
[all …]
H A Dgpio-ath79.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
7 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
45 static u32 ath79_gpio_read(struct ath79_gpio_ctrl *ctrl, unsigned reg) in ath79_gpio_read() argument
47 return readl(ctrl->base + reg); in ath79_gpio_read()
50 static void ath79_gpio_write(struct ath79_gpio_ctrl *ctrl, in ath79_gpio_write() argument
51 unsigned reg, u32 val) in ath79_gpio_write() argument
53 writel(val, ctrl->base + reg); in ath79_gpio_write()
57 struct ath79_gpio_ctrl *ctrl, unsigned reg, u32 mask, u32 bits) in ath79_gpio_update_bits() argument
61 old_val = ath79_gpio_read(ctrl, reg); in ath79_gpio_update_bits()
[all …]
/linux/arch/mips/sgi-ip22/
H A Dip22-nvram.c1 // SPDX-License-Identifier: GPL-2.0
3 * ip22-nvram.c: NVRAM and serial EEPROM handling.
5 * Copyright (C) 2003 Ladislav Michl (ladis@linux-mips.org)
56 static inline void eeprom_cmd(unsigned int *ctrl, unsigned cmd, unsigned reg) in eeprom_cmd() argument
61 ser_cmd = cmd | (reg << (16 - BITS_IN_COMMAND)); in eeprom_cmd()
64 __raw_writel(__raw_readl(ctrl) | EEPROM_DATO, ctrl); in eeprom_cmd()
66 __raw_writel(__raw_readl(ctrl) & ~EEPROM_DATO, ctrl); in eeprom_cmd()
67 __raw_writel(__raw_readl(ctrl) & ~EEPROM_ECLK, ctrl); in eeprom_cmd()
69 __raw_writel(__raw_readl(ctrl) | EEPROM_ECLK, ctrl); in eeprom_cmd()
74 __raw_writel(__raw_readl(ctrl) & ~EEPROM_DATO, ctrl); in eeprom_cmd()
[all …]
/linux/arch/m68k/include/asm/
H A Dm5407sim.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * m5407sim.h -- ColdFire 5407 System Integration Module support.
33 #define MCFSIM_PLLCR (MCF_MBAR + 0x08) /* PLL Ctrl */
34 #define MCFSIM_MPARK (MCF_MBAR + 0x0C) /* BUS Master Ctrl */
37 #define MCFSIM_AVR (MCF_MBAR + 0x4b) /* Autovector Ctrl */
38 #define MCFSIM_ICR0 (MCF_MBAR + 0x4c) /* Intr Ctrl reg 0 */
39 #define MCFSIM_ICR1 (MCF_MBAR + 0x4d) /* Intr Ctrl reg 1 */
40 #define MCFSIM_ICR2 (MCF_MBAR + 0x4e) /* Intr Ctrl reg 2 */
41 #define MCFSIM_ICR3 (MCF_MBAR + 0x4f) /* Intr Ctrl reg 3 */
42 #define MCFSIM_ICR4 (MCF_MBAR + 0x50) /* Intr Ctrl reg 4 */
[all …]
H A Dm5307sim.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * m5307sim.h -- ColdFire 5307 System Integration Module support.
27 #define MCFSIM_RSR (MCF_MBAR + 0x00) /* Reset Status reg */
33 #define MCFSIM_PLLCR (MCF_MBAR + 0x08) /* PLL Ctrl Reg */
34 #define MCFSIM_MPARK (MCF_MBAR + 0x0C) /* BUS Master Ctrl */
37 #define MCFSIM_AVR (MCF_MBAR + 0x4b) /* Autovector Ctrl */
38 #define MCFSIM_ICR0 (MCF_MBAR + 0x4c) /* Intr Ctrl reg 0 */
39 #define MCFSIM_ICR1 (MCF_MBAR + 0x4d) /* Intr Ctrl reg 1 */
40 #define MCFSIM_ICR2 (MCF_MBAR + 0x4e) /* Intr Ctrl reg 2 */
41 #define MCFSIM_ICR3 (MCF_MBAR + 0x4f) /* Intr Ctrl reg 3 */
[all …]
H A Dm5206sim.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * m5206sim.h -- ColdFire 5206 System Integration Module support.
25 #define MCFSIM_SIMR (MCF_MBAR + 0x03) /* SIM Config reg */
26 #define MCFSIM_ICR1 (MCF_MBAR + 0x14) /* Intr Ctrl reg 1 */
27 #define MCFSIM_ICR2 (MCF_MBAR + 0x15) /* Intr Ctrl reg 2 */
28 #define MCFSIM_ICR3 (MCF_MBAR + 0x16) /* Intr Ctrl reg 3 */
29 #define MCFSIM_ICR4 (MCF_MBAR + 0x17) /* Intr Ctrl reg 4 */
30 #define MCFSIM_ICR5 (MCF_MBAR + 0x18) /* Intr Ctrl reg 5 */
31 #define MCFSIM_ICR6 (MCF_MBAR + 0x19) /* Intr Ctrl reg 6 */
32 #define MCFSIM_ICR7 (MCF_MBAR + 0x1a) /* Intr Ctrl reg 7 */
[all …]
/linux/arch/arm64/include/asm/
H A Dhw_breakpoint.h1 /* SPDX-License-Identifier: GPL-2.0-only */
24 struct arch_hw_breakpoint_ctrl ctrl; member
33 static inline u32 encode_ctrl_reg(struct arch_hw_breakpoint_ctrl ctrl) in encode_ctrl_reg() argument
35 u32 val = (ctrl.len << 5) | (ctrl.type << 3) | (ctrl.privilege << 1) | in encode_ctrl_reg()
36 ctrl.enabled; in encode_ctrl_reg()
38 if (is_kernel_in_hyp_mode() && ctrl.privilege == AARCH64_BREAKPOINT_EL1) in encode_ctrl_reg()
44 static inline void decode_ctrl_reg(u32 reg, in decode_ctrl_reg() argument
45 struct arch_hw_breakpoint_ctrl *ctrl) in decode_ctrl_reg() argument
47 ctrl->enabled = reg & 0x1; in decode_ctrl_reg()
48 reg >>= 1; in decode_ctrl_reg()
[all …]
/linux/arch/arm/include/asm/
H A Dhw_breakpoint.h1 /* SPDX-License-Identifier: GPL-2.0 */
25 struct arch_hw_breakpoint_ctrl ctrl; member
28 static inline u32 encode_ctrl_reg(struct arch_hw_breakpoint_ctrl ctrl) in encode_ctrl_reg() argument
30 return (ctrl.mismatch << 22) | (ctrl.len << 5) | (ctrl.type << 3) | in encode_ctrl_reg()
31 (ctrl.privilege << 1) | ctrl.enabled; in encode_ctrl_reg()
34 static inline void decode_ctrl_reg(u32 reg, in decode_ctrl_reg() argument
35 struct arch_hw_breakpoint_ctrl *ctrl) in decode_ctrl_reg() argument
37 ctrl->enabled = reg & 0x1; in decode_ctrl_reg()
38 reg >>= 1; in decode_ctrl_reg()
39 ctrl->privilege = reg & 0x3; in decode_ctrl_reg()
[all …]
/linux/arch/arm/kernel/
H A Dunwind.c1 // SPDX-License-Identifier: GPL-2.0-only
90 /* sign-extend to 32 bits */ \
101 * stop - 1 = last entry
125 addr_prel31 = (addr - (unsigned long)start) & 0x7fffffff; in search_index()
127 while (start < stop - 1) { in search_index()
128 const struct unwind_idx *mid = start + ((stop - start) >> 1); in search_index()
134 if (addr_prel31 - ((unsigned long)mid - (unsigned long)start) < in search_index()
135 mid->addr_offset) in search_index()
139 addr_prel31 -= ((unsigned long)mid - in search_index()
145 if (likely(start->addr_offset <= addr_prel31)) in search_index()
[all …]
/linux/drivers/mtd/nand/raw/
H A Dtegra_nand.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2014-2015 Lucas Stach <dev@lynxeye.de>
10 #include <linux/dma-mapping.h>
34 #define COMMAND_TRANS_SIZE(size) ((((size) - 1) & 0xf) << 20)
40 #define COMMAND_CLE_SIZE(size) ((((size) - 1) & 0x3) << 4)
41 #define COMMAND_ALE_SIZE(size) ((((size) - 1) & 0xf) << 0)
156 #define OFFSET(val, off) ((val) < (off) ? 0 : (val) - (off))
207 int bytes_per_step = DIV_ROUND_UP(BITS_PER_STEP_RS * chip->ecc.strength, in tegra_nand_ooblayout_rs_ecc()
211 return -ERANGE; in tegra_nand_ooblayout_rs_ecc()
213 oobregion->offset = SKIP_SPARE_BYTES; in tegra_nand_ooblayout_rs_ecc()
[all …]
/linux/drivers/media/i2c/s5c73m3/
H A Ds5c73m3-ctrls.c1 // SPDX-License-Identifier: GPL-2.0-only
21 #include <media/media-entity.h>
22 #include <media/v4l2-ctrls.h>
23 #include <media/v4l2-device.h>
24 #include <media/v4l2-subdev.h>
25 #include <media/v4l2-mediabus.h>
29 static int s5c73m3_get_af_status(struct s5c73m3 *state, struct v4l2_ctrl *ctrl) in s5c73m3_get_af_status() argument
31 u16 reg = REG_AF_STATUS_UNFOCUSED; in s5c73m3_get_af_status() local
33 int ret = s5c73m3_read(state, REG_AF_STATUS, &reg); in s5c73m3_get_af_status()
35 switch (reg) { in s5c73m3_get_af_status()
[all …]
/linux/drivers/spi/
H A Dspi-realtek-rtl.c1 // SPDX-License-Identifier: GPL-2.0-only
29 #define REG(x) (rtspi->base + x) macro
34 struct rtspi *rtspi = spi_controller_get_devdata(spi->controller); in rt_set_cs()
38 value = __raw_readl(REG(RTL_SPI_SFCSR)); in rt_set_cs()
43 __raw_writel(value, REG(RTL_SPI_SFCSR)); in rt_set_cs()
50 value = __raw_readl(REG(RTL_SPI_SFCSR)); in set_size()
56 __raw_writel(value, REG(RTL_SPI_SFCSR)); in set_size()
61 while (!(__raw_readl(REG(RTL_SPI_SFCSR)) & RTL_SPI_SFCSR_RDY)) in wait_ready()
68 __raw_writel(*buf, REG(RTL_SPI_SFDR)); in send4()
75 __raw_writel(buf[0] << 24, REG(RTL_SPI_SFDR)); in send1()
[all …]
/linux/drivers/platform/surface/aggregator/
H A Dcontroller.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2019-2022 Maximilian Luz <luzmaximilian@gmail.com>
38 /* -- Safe counters. -------------------------------------------------------- */
41 * ssh_seq_reset() - Reset/initialize sequence ID counter.
46 WRITE_ONCE(c->value, 0); in ssh_seq_reset()
50 * ssh_seq_next() - Get next sequence ID.
57 u8 old = READ_ONCE(c->value); in ssh_seq_next()
61 while (unlikely((ret = cmpxchg(&c->value, old, new)) != old)) { in ssh_seq_next()
70 * ssh_rqid_reset() - Reset/initialize request ID counter.
75 WRITE_ONCE(c->value, 0); in ssh_rqid_reset()
[all …]
/linux/drivers/usb/dwc3/
H A Dep0.c1 // SPDX-License-Identifier: GPL-2.0
3 * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
19 #include <linux/dma-mapping.h>
34 struct usb_ctrlrequest *ctrl);
42 dwc = dep->dwc; in dwc3_ep0_prepare_one_trb()
43 trb = &dwc->ep0_trb[dep->trb_enqueue]; in dwc3_ep0_prepare_one_trb()
46 dep->trb_enqueue++; in dwc3_ep0_prepare_one_trb()
48 trb->bpl = lower_32_bits(buf_dma); in dwc3_ep0_prepare_one_trb()
49 trb->bph = upper_32_bits(buf_dma); in dwc3_ep0_prepare_one_trb()
[all …]
/linux/Documentation/devicetree/bindings/arm/bcm/
H A Dbrcm,brcmstb.txt2 -----------------------------------------------
3 Boards with Broadcom Brahma15 ARM-based BCMxxxx (generally BCM7xxx variants)
7 - compatible: "brcm,bcm<chip_id>", "brcm,brcmstb"
11 #address-cells = <2>;
12 #size-cells = <2>;
16 Further, syscon nodes that map platform-specific registers used for general
19 - compatible: "brcm,bcm<chip_id>-sun-top-ctrl", "syscon"
20 - compatible: "brcm,bcm<chip_id>-cpu-biu-ctrl",
21 "brcm,brcmstb-cpu-biu-ctrl",
23 - compatible: "brcm,bcm<chip_id>-hif-continuation", "syscon"
[all …]
/linux/arch/loongarch/include/asm/
H A Dhw_breakpoint.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2022-2023 Loongson Technology Corporation Limited
28 struct arch_hw_breakpoint_ctrl ctrl; member
53 #define LOONGARCH_CSR_NAME_CTRL CTRL
57 #define LOONGARCH_CSR_WATCH_READ(N, REG, T, VAL) \ argument
60 VAL = csr_read64(LOONGARCH_CSR_##IB##N##REG); \
62 VAL = csr_read64(LOONGARCH_CSR_##DB##N##REG); \
65 #define LOONGARCH_CSR_WATCH_WRITE(N, REG, T, VAL) \ argument
68 csr_write64(VAL, LOONGARCH_CSR_##IB##N##REG); \
70 csr_write64(VAL, LOONGARCH_CSR_##DB##N##REG); \
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Ddavinci_emac.txt7 - compatible: "ti,davinci-dm6467-emac", "ti,am3517-emac" or
8 "ti,dm816-emac"
9 - reg: Offset and length of the register set for the device
10 - ti,davinci-ctrl-reg-offset: offset to control register
11 - ti,davinci-ctrl-mod-reg-offset: offset to control module register
12 - ti,davinci-ctrl-ram-offset: offset to control module ram
13 - ti,davinci-ctrl-ram-size: size of control module ram
14 - interrupts: interrupt mapping for the davinci emac interrupts sources:
21 - phy-handle: See ethernet.txt file in the same directory.
23 - ti,davinci-rmii-en: 1 byte, 1 means use RMII
[all …]
/linux/drivers/mmc/host/
H A Dsdhci_f_sdh30.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2013 - 2015 Fujitsu Semiconductor, Ltd
20 #include "sdhci-pltfm.h"
42 u32 ctrl = 0; in sdhci_f_sdh30_soft_voltage_switch() local
45 ctrl = sdhci_readl(host, F_SDH30_IO_CONTROL2); in sdhci_f_sdh30_soft_voltage_switch()
46 ctrl |= F_SDH30_CRES_O_DN; in sdhci_f_sdh30_soft_voltage_switch()
47 sdhci_writel(host, ctrl, F_SDH30_IO_CONTROL2); in sdhci_f_sdh30_soft_voltage_switch()
48 ctrl |= F_SDH30_MSEL_O_1_8; in sdhci_f_sdh30_soft_voltage_switch()
49 sdhci_writel(host, ctrl, F_SDH30_IO_CONTROL2); in sdhci_f_sdh30_soft_voltage_switch()
51 ctrl &= ~F_SDH30_CRES_O_DN; in sdhci_f_sdh30_soft_voltage_switch()
[all …]
/linux/drivers/spmi/
H A Dspmi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
16 #include <dt-bindings/spmi/spmi.h>
36 struct spmi_controller *ctrl = to_spmi_controller(dev); in spmi_ctrl_release() local
38 ida_free(&ctrl_ida, ctrl->nr); in spmi_ctrl_release()
39 kfree(ctrl); in spmi_ctrl_release()
51 if (drv->name) in spmi_device_match()
52 return strncmp(dev_name(dev), drv->name, in spmi_device_match()
59 * spmi_device_add() - add a device previously constructed via spmi_device_alloc()
64 struct spmi_controller *ctrl = sdev->ctrl; in spmi_device_add() local
[all …]
/linux/drivers/net/can/c_can/
H A Dc_can_platform.c9 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix <s.hauer@pengutronix.de>
10 * - Simon Kallweit, intefo AG <simon.kallweit@intefo.ch>
47 /* 16-bit c_can registers can be arranged differently in the memory
48 * architecture of different implementations. For example: 16-bit
49 * registers can be aligned to a 16-bit boundary or 32-bit boundary etc.
53 enum reg index) in c_can_plat_read_reg_aligned_to_16bit()
55 return readw(priv->base + priv->regs[index]); in c_can_plat_read_reg_aligned_to_16bit()
59 enum reg index, u16 val) in c_can_plat_write_reg_aligned_to_16bit()
61 writew(val, priv->base + priv->regs[index]); in c_can_plat_write_reg_aligned_to_16bit()
65 enum reg index) in c_can_plat_read_reg_aligned_to_32bit()
[all …]

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