Searched +full:cti +full:- +full:ctm +full:- +full:id (Results 1 – 3 of 3) sorted by relevance
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause4 ---5 $id[all...]
1 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause4 ---5 $id: http://devicetree.org/schemas/arm/coresight-cti.yaml#6 $schema: http://devicetree.org/meta-schemas/core.yaml#8 title: ARM Coresight Cross Trigger Interface (CTI) device.11 The CoreSight Embedded Cross Trigger (ECT) consists of CTI devices connected13 a star topology via the Cross Trigger Matrix (CTM), which is not programmable.18 The CTI component properties define the connections between the individual19 CTI and the components it is directly connected to, consisting of input and21 output hardware trigger signals (8 each for v1 CTI, 32 each for v2 CTI). The[all …]
1 /*-10 found at http://www.gnu.org/licenses/gpl-2.0.html101 /* [0x6c] Read-only that reflects CPU Cluster Local GIC base high address */103 /* [0x70] Read-only that reflects CPU Cluster Local GIC base low address */105 /* [0x74] Read-only that reflects the device's IOGIC base high address. */107 /* [0x78] Read-only that reflects IOGIC base low address */480 /* Value read in the Cluster ID Affinity Level-1 field, bits[15:8], of the Multiprocessor Affinity485 /* Value read in the Cluster ID Affinity Level-2 field, bits[23:16], of the Multiprocessor Affinity512 By default, CPU0 only exits poreset when the CPUs cluster exits power-on-reset and then kicks other…513 …t by primary CPU as part of the initialization process will initiate power-on-reset to this specif…[all …]