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/linux/drivers/media/platform/ti/vpe/
H A Dcsc.c20 #include "csc.h"
110 void csc_dump_regs(struct csc_data *csc) in csc_dump_regs() argument
112 struct device *dev = &csc->pdev->dev; in csc_dump_regs()
115 ioread32(csc->base + CSC_##r)) in csc_dump_regs()
117 dev_dbg(dev, "CSC Registers @ %pa:\n", &csc->res->start); in csc_dump_regs()
130 void csc_set_coeff_bypass(struct csc_data *csc, u32 *csc_reg5) in csc_set_coeff_bypass() argument
139 void csc_set_coeff(struct csc_data *csc, u32 *csc_reg0, in csc_set_coeff() argument
249 struct csc_data *csc; in csc_create() local
253 csc = devm_kzalloc(&pdev->dev, sizeof(*csc), GFP_KERNEL); in csc_create()
254 if (!csc) { in csc_create()
[all …]
H A DMakefile5 obj-$(CONFIG_VIDEO_TI_CSC) += ti-csc.o
10 ti-csc-y := csc.o
H A Dcsc.h58 void csc_dump_regs(struct csc_data *csc);
59 void csc_set_coeff_bypass(struct csc_data *csc, u32 *csc_reg5);
60 void csc_set_coeff(struct csc_data *csc, u32 *csc_reg0,
/linux/drivers/gpu/ipu-v3/
H A Dipu-ic-csc.c355 static int calc_csc_coeffs(struct ipu_ic_csc *csc) in calc_csc_coeffs() argument
360 tbl_idx = (QUANT_MAP(csc->in_cs.quant) << 1) | in calc_csc_coeffs()
361 QUANT_MAP(csc->out_cs.quant); in calc_csc_coeffs()
363 if (csc->in_cs.cs == csc->out_cs.cs) { in calc_csc_coeffs()
364 csc->params = (csc->in_cs.cs == IPUV3_COLORSPACE_YUV) ? in calc_csc_coeffs()
372 switch (csc->out_cs.enc) { in calc_csc_coeffs()
374 params_tbl = (csc->in_cs.cs == IPUV3_COLORSPACE_YUV) ? in calc_csc_coeffs()
378 params_tbl = (csc->in_cs.cs == IPUV3_COLORSPACE_YUV) ? in calc_csc_coeffs()
385 csc->params = *params_tbl[tbl_idx]; in calc_csc_coeffs()
390 int __ipu_ic_calc_csc(struct ipu_ic_csc *csc) in __ipu_ic_calc_csc() argument
[all …]
H A Dipu-dp.c273 u32 reg, csc; in ipu_dp_disable_channel() local
283 csc = reg & DP_COM_CONF_CSC_DEF_MASK; in ipu_dp_disable_channel()
285 if (csc == DP_COM_CONF_CSC_DEF_BOTH || csc == DP_COM_CONF_CSC_DEF_BG) in ipu_dp_disable_channel()
/linux/drivers/gpu/drm/tidss/
H A Dtidss_dispc.c1415 /* CSC */
1435 void (*to_regval)(const struct dispc_csc_coef *csc, u32 *regval);
1446 void dispc_csc_offset_regval(const struct dispc_csc_coef *csc, u32 *regval) in dispc_csc_offset_regval() argument
1449 regval[5] = OVAL(csc->preoffset[0], csc->preoffset[1]); in dispc_csc_offset_regval()
1450 regval[6] = OVAL(csc->preoffset[2], csc->postoffset[0]); in dispc_csc_offset_regval()
1451 regval[7] = OVAL(csc->postoffset[1], csc->postoffset[2]); in dispc_csc_offset_regval()
1457 void dispc_csc_yuv2rgb_regval(const struct dispc_csc_coef *csc, u32 *regval) in dispc_csc_yuv2rgb_regval() argument
1459 regval[0] = CVAL(csc->m[CSC_RY], csc->m[CSC_RCR]); in dispc_csc_yuv2rgb_regval()
1460 regval[1] = CVAL(csc->m[CSC_RCB], csc->m[CSC_GY]); in dispc_csc_yuv2rgb_regval()
1461 regval[2] = CVAL(csc->m[CSC_GCR], csc->m[CSC_GCB]); in dispc_csc_yuv2rgb_regval()
[all …]
/linux/drivers/gpu/drm/msm/disp/mdp4/
H A Dmdp4_plane.c166 enum mdp4_pipe pipe, struct csc_cfg *csc) in mdp4_write_csc_config() argument
170 for (i = 0; i < ARRAY_SIZE(csc->matrix); i++) { in mdp4_write_csc_config()
172 csc->matrix[i]); in mdp4_write_csc_config()
175 for (i = 0; i < ARRAY_SIZE(csc->post_bias) ; i++) { in mdp4_write_csc_config()
177 csc->pre_bias[i]); in mdp4_write_csc_config()
180 csc->post_bias[i]); in mdp4_write_csc_config()
183 for (i = 0; i < ARRAY_SIZE(csc->post_clamp) ; i++) { in mdp4_write_csc_config()
185 csc->pre_clamp[i]); in mdp4_write_csc_config()
188 csc->post_clamp[i]); in mdp4_write_csc_config()
322 struct csc_cfg *csc = mdp_get_default_csc_cfg(CSC_YUV2RGB); in mdp4_plane_mode_set() local
[all …]
/linux/Documentation/userspace-api/media/v4l/
H A Dvidioc-subdev-enum-mbus-code.rst118 ioctl with :ref:`V4L2_MBUS_FRAMEFMT_SET_CSC <mbus-framefmt-set-csc>` set.
125 ioctl with :ref:`V4L2_MBUS_FRAMEFMT_SET_CSC <mbus-framefmt-set-csc>` set.
132 ioctl with :ref:`V4L2_MBUS_FRAMEFMT_SET_CSC <mbus-framefmt-set-csc>` set.
139 ioctl with :ref:`V4L2_MBUS_FRAMEFMT_SET_CSC <mbus-framefmt-set-csc>` set.
146 ioctl with :ref:`V4L2_MBUS_FRAMEFMT_SET_CSC <mbus-framefmt-set-csc>` set.
/linux/Documentation/devicetree/bindings/media/
H A Dti,vpe.yaml26 - description: Color Space Conversion (CSC) register region
33 - const: csc
59 "csc",
/linux/drivers/media/platform/microchip/
H A Dmicrochip-sama7g5-isc.c9 * Sensor-->PFE-->DPC-->WB-->CFA-->CC-->GAM-->VHXS-->CSC-->CBHS-->SUB-->RLP-->DMA-->HIS
20 * CSC: Programmable color space conversion
235 regmap_write(regmap, ISC_CSC_YR_YG + isc->offsets.csc, in isc_sama7g5_config_csc()
237 regmap_write(regmap, ISC_CSC_YB_OY + isc->offsets.csc, in isc_sama7g5_config_csc()
239 regmap_write(regmap, ISC_CSC_CBR_CBG + isc->offsets.csc, in isc_sama7g5_config_csc()
241 regmap_write(regmap, ISC_CSC_CBB_OCB + isc->offsets.csc, in isc_sama7g5_config_csc()
243 regmap_write(regmap, ISC_CSC_CRR_CRG + isc->offsets.csc, in isc_sama7g5_config_csc()
245 regmap_write(regmap, ISC_CSC_CRB_OCR + isc->offsets.csc, in isc_sama7g5_config_csc()
448 isc->offsets.csc = ISC_SAMA7G5_CSC_OFFSET; in microchip_xisc_probe()
H A Dmicrochip-sama5d2-isc.c11 * Sensor-->PFE-->WB-->CFA-->CC-->GAM-->CSC-->CBC-->SUB-->RLP-->DMA
19 * CSC: Programmable color space conversion
222 regmap_write(regmap, ISC_CSC_YR_YG + isc->offsets.csc, in isc_sama5d2_config_csc()
224 regmap_write(regmap, ISC_CSC_YB_OY + isc->offsets.csc, in isc_sama5d2_config_csc()
226 regmap_write(regmap, ISC_CSC_CBR_CBG + isc->offsets.csc, in isc_sama5d2_config_csc()
228 regmap_write(regmap, ISC_CSC_CBB_OCB + isc->offsets.csc, in isc_sama5d2_config_csc()
230 regmap_write(regmap, ISC_CSC_CRR_CRG + isc->offsets.csc, in isc_sama5d2_config_csc()
232 regmap_write(regmap, ISC_CSC_CRB_OCR + isc->offsets.csc, in isc_sama5d2_config_csc()
459 isc->offsets.csc = ISC_SAMA5D2_CSC_OFFSET; in microchip_isc_probe()
H A Dmicrochip-isc.h165 * @csc: Offset for the CSC register
176 u32 csc; member
251 * specific CSC module
/linux/drivers/gpu/drm/sun4i/
H A Dsun8i_csc.c51 * DE3 has a bit different CSC units. Factors are in two's complement format.
62 * Please note that above formula is true only for Blender CSC. Other DE3 CSC
138 DRM_WARN("Wrong CSC mode specified.\n"); in sun8i_csc_set_coefficients()
176 DRM_WARN("Wrong CSC mode specified.\n"); in sun8i_de3_ccsc_set_coefficients()
/linux/drivers/gpu/drm/nouveau/dispnv50/
H A Dbase907c.c144 u32 *val = &asyw->csc.matrix[j * 4 + i]; in base907c_csc()
146 * HW CSC does. Skip it. */ in base907c_csc()
181 NVVAL(NV907C, SET_CSC_RED2RED, COEFF, asyw->csc.matrix[0]), in base907c_csc_set()
183 SET_CSC_GRN2RED, &asyw->csc.matrix[1], 11); in base907c_csc_set()
198 .csc = base907c_csc,
/linux/drivers/gpu/drm/vc4/
H A Dvc4_hvs.c1425 u32 csc[3][5]; member
1431 .csc = {
1438 .csc = {
1445 .csc = {
1454 .csc = {
1461 .csc = {
1468 .csc = {
1495 HVS_WRITE(CFC1_N_MA_CSC_COEFF_C00(i), coeffs->csc[0][0]); in vc6_hvs_hw_init()
1496 HVS_WRITE(CFC1_N_MA_CSC_COEFF_C01(i), coeffs->csc[0][1]); in vc6_hvs_hw_init()
1497 HVS_WRITE(CFC1_N_MA_CSC_COEFF_C02(i), coeffs->csc[0][2]); in vc6_hvs_hw_init()
[all …]
/linux/Documentation/devicetree/bindings/display/
H A Dbrcm,bcm2711-hdmi.yaml28 - description: CSC register range
40 - const: csc
134 "csc",
/linux/arch/powerpc/boot/
H A Dmvme5100.c5 * Author: Stephen Chivers <schivers@csc.com>
7 * Copyright 2013 CSC Australia Pty. Ltd.
/linux/drivers/pcmcia/
H A Di82092.c310 int csc; in i82092aa_interrupt() local
317 csc = indirect_read(i, I365_CSC); in i82092aa_interrupt()
319 if (csc == 0) /* no events on this socket */ in i82092aa_interrupt()
324 if (csc & I365_CSC_DETECT) { in i82092aa_interrupt()
332 if (csc & I365_CSC_STSCHG) in i82092aa_interrupt()
336 if (csc & I365_CSC_BVD1) in i82092aa_interrupt()
338 if (csc & I365_CSC_BVD2) in i82092aa_interrupt()
340 if (csc & I365_CSC_READY) in i82092aa_interrupt()
H A Dyenta_socket.c374 /* CSC interrupt: no ISA irq for CSC */ in yenta_set_socket()
512 u8 csc; in yenta_interrupt() local
519 csc = exca_readb(socket, I365_CSC); in yenta_interrupt()
521 if (!(cb_event || csc)) in yenta_interrupt()
525 events |= (csc & I365_CSC_DETECT) ? SS_DETECT : 0; in yenta_interrupt()
527 events |= (csc & I365_CSC_STSCHG) ? SS_STSCHG : 0; in yenta_interrupt()
529 events |= (csc & I365_CSC_BVD1) ? SS_BATDEAD : 0; in yenta_interrupt()
530 events |= (csc & I365_CSC_BVD2) ? SS_BATWARN : 0; in yenta_interrupt()
531 events |= (csc & I365_CSC_READY) ? SS_READY : 0; in yenta_interrupt()
596 /* Re-enable CSC interrupts */ in yenta_sock_init()
[all …]
H A Dpd6729.c192 unsigned int csc; in pd6729_interrupt() local
195 csc = indirect_read(&socket[i], I365_CSC); in pd6729_interrupt()
196 if (csc == 0) /* no events on this socket */ in pd6729_interrupt()
202 if (csc & I365_CSC_DETECT) { in pd6729_interrupt()
211 events |= (csc & I365_CSC_STSCHG) in pd6729_interrupt()
215 events |= (csc & I365_CSC_BVD1) in pd6729_interrupt()
217 events |= (csc & I365_CSC_BVD2) in pd6729_interrupt()
219 events |= (csc & I365_CSC_READY) in pd6729_interrupt()
/linux/drivers/staging/media/deprecated/atmel/
H A Datmel-isc.h164 * @csc: Offset for the CSC register
175 u32 csc; member
240 * specific CSC module
/linux/drivers/media/platform/ti/omap3isp/
H A Disppreview.c36 { /* CSC Coef Matrix */
40 }, /* CSC Offset */
400 const struct omap3isp_prev_csc *csc = &params->csc; in preview_config_csc() local
403 val = (csc->matrix[0][0] & 0x3ff) << ISPPRV_CSC0_RY_SHIFT; in preview_config_csc()
404 val |= (csc->matrix[0][1] & 0x3ff) << ISPPRV_CSC0_GY_SHIFT; in preview_config_csc()
405 val |= (csc->matrix[0][2] & 0x3ff) << ISPPRV_CSC0_BY_SHIFT; in preview_config_csc()
408 val = (csc->matrix[1][0] & 0x3ff) << ISPPRV_CSC1_RCB_SHIFT; in preview_config_csc()
409 val |= (csc->matrix[1][1] & 0x3ff) << ISPPRV_CSC1_GCB_SHIFT; in preview_config_csc()
410 val |= (csc->matrix[1][2] & 0x3ff) << ISPPRV_CSC1_BCB_SHIFT; in preview_config_csc()
413 val = (csc->matrix[2][0] & 0x3ff) << ISPPRV_CSC2_RCR_SHIFT; in preview_config_csc()
[all …]
H A Disppreview.h71 * @csc: Color space conversion (RGB to YCbCr) parameters.
90 struct omap3isp_prev_csc csc; member
/linux/drivers/gpu/drm/amd/display/dc/mpc/dcn20/
H A Ddcn20_mpc.c151 /* determine which CSC coefficients (A or B) we are using in mpc2_set_output_csc()
153 * the CSC update so CSC is updated on frame boundary in mpc2_set_output_csc()
209 /* determine which CSC coefficients (A or B) we are using in mpc2_set_ocsc_default()
211 * the CSC update so CSC is updated on frame boundary in mpc2_set_ocsc_default()
/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn10/
H A Ddcn10_dpp_cm.c265 /* determine which CSC matrix (ocsc or comb) we are using in dpp1_cm_program_color_matrix()
267 * the CSC update so CSC is updated on frame boundary in dpp1_cm_program_color_matrix()
523 /* determine which CSC matrix (icsc or coma) we are using in dpp1_program_input_csc()
525 * the CSC update so CSC is updated on frame boundary in dpp1_program_input_csc()

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