Home
last modified time | relevance | path

Searched +full:crypto +full:- +full:engine (Results 1 – 25 of 125) sorted by relevance

12345

/linux/drivers/crypto/aspeed/
H A DKconfig2 tristate "Support for Aspeed cryptographic engine driver"
6 Hash and Crypto Engine (HACE) is designed to accelerate the
13 bool "Enable Aspeed crypto debug messages"
16 Print Aspeed crypto debugging messages if you use this
22 bool "Enable Aspeed Hash & Crypto Engine (HACE) hash"
29 Select here to enable Aspeed Hash & Crypto Engine (HACE)
32 SHA-1, SHA-224, SHA-256, SHA-384, SHA-512, and so on.
35 bool "Enable Aspeed Hash & Crypto Engine (HACE) crypto"
43 Select here to enable Aspeed Hash & Crypto Engine (HACE)
44 crypto driver.
[all …]
/linux/Documentation/devicetree/bindings/firmware/
H A Dintel,ixp4xx-network-processing-engine.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/firmware/intel,ixp4xx-network-processing-engine.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Intel IXP4xx Network Processing Engine
11 - Linus Walleij <linusw@kernel.org>
14 On the IXP4xx SoCs, the Network Processing Engine (NPE) is a small
16 and crypto tasks. It also manages the MDIO bus to the ethernet PHYs
24 - items:
25 - const: intel,ixp4xx-network-processing-engine
[all …]
/linux/Documentation/devicetree/bindings/crypto/
H A Dintel,ixp4xx-crypto.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/crypto/intel,ixp4xx-crypto.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Intel IXP4xx cryptographic engine
11 - Linus Walleij <linusw@kernel.org>
14 The Intel IXP4xx cryptographic engine makes use of the IXP4xx NPE
15 (Network Processing Engine). Since it is not a device on its own
16 it is defined as a subnode of the NPE, if crypto support is
21 const: intel,ixp4xx-crypto
[all …]
H A Daspeed,ast2500-hace.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/crypto/aspeed,ast2500-hace.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ASPEED HACE hash and crypto Hardware Accelerator Engines
10 - Neal Liu <neal_liu@aspeedtech.com>
13 The Hash and Crypto Engine (HACE) is designed to accelerate the throughput
15 divided into two independently engines - Hash Engine and Crypto Engine.
20 - aspeed,ast2500-hace
21 - aspeed,ast2600-hace
[all …]
H A Dqcom-qce.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/crypto/qcom-qce.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm crypto engine driver
10 - Bjorn Andersson <andersson@kernel.org>
11 - Konrad Dybcio <konradybcio@kernel.org>
14 This document defines the binding for the QCE crypto
20 - const: qcom,crypto-v5.1
24 - const: qcom,crypto-v5.4
[all …]
H A Dallwinner,sun4i-a10-crypto.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/crypto/allwinner,sun4i-a10-crypto.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
16 - const: allwinner,sun4i-a10-crypto
17 - items:
18 - const: allwinner,sun5i-a13-crypto
19 - const: allwinner,sun4i-a10-crypto
[all …]
H A Dallwinner,sun8i-ce.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/crypto/allwinner,sun8i-ce.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner Crypto Engine driver
10 - Corentin Labbe <clabbe.montjoie@gmail.com>
15 - allwinner,sun8i-h3-crypto
16 - allwinner,sun8i-r40-crypto
17 - allwinner,sun20i-d1-crypto
18 - allwinner,sun50i-a64-crypto
[all …]
H A Dnvidia,tegra234-se-aes.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/crypto/nvidia,tegra234-se-aes.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra Security Engine for AES algorithms
10 The Tegra Security Engine accelerates the following AES encryption/decryption
11 algorithms - AES-ECB, AES-CBC, AES-OFB, AES-XTS, AES-CTR, AES-GCM, AES-CCM,
12 AES-CMAC
15 - Akhil R <akhilrajeev@nvidia.com>
19 const: nvidia,tegra234-se-aes
[all …]
H A Dnvidia,tegra234-se-hash.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/crypto/nvidia,tegra234-se-hash.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra Security Engine for HASH algorithms
10 The Tegra Security HASH Engine accelerates the following HASH functions -
11 SHA1, SHA224, SHA256, SHA384, SHA512, SHA3-224, SHA3-256, SHA3-384, SHA3-512
15 - Akhil R <akhilrajeev@nvidia.com>
19 const: nvidia,tegra234-se-hash
30 dma-coherent: true
[all …]
H A Damlogic,gxl-crypto.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/crypto/amlogic,gxl-crypto.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Corentin Labbe <clabbe@baylibre.com>
15 - const: amlogic,gxl-crypto
22 - description: Interrupt for flow 0
23 - description: Interrupt for flow 1
28 clock-names:
32 - compatible
[all …]
/linux/drivers/crypto/
H A Dsa2ul.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * K3 SA2UL crypto accelerator driver
5 * Copyright (C) 2018-2020 Texas Instruments Incorporated - http://www.ti.com
15 #include <crypto/aes.h>
16 #include <crypto/sha1.h>
17 #include <crypto/sha2.h>
35 * Encoding used to identify the typo of crypto operation
62 ((ctx_sz) ? ((ctx_sz) / 32 - 1) : 0)
70 /* Next Engine Select code in CP_ACE */
71 #define SA_ENG_ID_EM1 2 /* Enc/Dec engine with AES/DEC core */
[all …]
/linux/drivers/crypto/amlogic/
H A Damlogic-gxl.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * amlogic.h - hardware cryptographic offloader for Amlogic SoC
5 * Copyright (C) 2018-2019 Corentin LABBE <clabbe@baylibre.com>
7 #include <crypto/aes.h>
8 #include <crypto/engine.h>
9 #include <crypto/skcipher.h>
11 #include <linux/crypto.h>
34 * struct meson_desc - Descriptor for DMA operations
40 * @len: 0-16 length of data to operate
44 * @mode: 20-23 Type of algorithm (AES, SHA)
[all …]
/linux/drivers/soc/qcom/
H A Dice.c1 // SPDX-License-Identifier: GPL-2.0
3 * Qualcomm ICE (Inline Crypto Engine) support.
5 * Copyright (c) 2013-2019, The Linux Foundation. All rights reserved.
95 #define qcom_ice_writel(engine, val, reg) \ argument
96 writel((val), (engine)->base + (reg))
98 #define qcom_ice_readl(engine, reg) \ argument
99 readl((engine)->base + (reg))
119 struct device *dev = ice->dev; in qcom_ice_check_supported()
136 ice->hwkm_version = QCOM_ICE_HWKM_V2; in qcom_ice_check_supported()
138 ice->hwkm_version = QCOM_ICE_HWKM_V1; in qcom_ice_check_supported()
[all …]
/linux/Documentation/arch/powerpc/
H A Dvas-api.rst1 .. SPDX-License-Identifier: GPL-2.0
2 .. _VAS-API:
12 allows both userspace and kernel communicate to co-processor
14 unit comprises of one or more hardware engines or co-processor types
16 userspace applications will have access to only GZIP Compression engine
21 Requests to the GZIP engine must be formatted as a co-processor Request
24 the engine's request queue.
26 The GZIP engine provides two priority levels of requests: Normal and
37 Application access to the GZIP engine is provided through
38 /dev/crypto/nx-gzip device node implemented by the VAS/NX device driver.
[all …]
/linux/drivers/crypto/gemini/
H A Dsl3516-ce.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * sl3516-ce.h - hardware cryptographic offloader for cortina/gemini SoC
8 * Called either Crypto Acceleration Engine Module, Security Acceleration Engine
9 * or IPSEC module in the datasheet, it will be called Crypto Engine for short
16 #include <crypto/aes.h>
17 #include <crypto/engine.h>
18 #include <crypto/scatterwalk.h>
19 #include <crypto/skcipher.h>
90 * struct sl3516_ce_descriptor - descriptor for CE operations
100 * struct desc_frame_ctrl - Information for the current descriptor
[all …]
H A Dsl3516-ce-rng.c1 // SPDX-License-Identifier: GPL-2.0
3 * sl3516-ce-rng.c - hardware cryptographic offloader for SL3516 SoC.
7 * This file handle the RNG found in the SL3516 crypto engine
9 #include "sl3516-ce.h"
23 ce->hwrng_stat_req++; in sl3516_ce_rng_read()
24 ce->hwrng_stat_bytes += max; in sl3516_ce_rng_read()
27 err = pm_runtime_get_sync(ce->dev); in sl3516_ce_rng_read()
29 pm_runtime_put_noidle(ce->dev); in sl3516_ce_rng_read()
34 *data = readl(ce->base + IPSEC_RAND_NUM_REG); in sl3516_ce_rng_read()
39 pm_runtime_put(ce->dev); in sl3516_ce_rng_read()
[all …]
/linux/drivers/dma/idxd/
H A Ddefaults.c1 // SPDX-License-Identifier: GPL-2.0
8 struct idxd_engine *engine; in idxd_load_iaa_device_defaults() local
12 if (!test_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags)) in idxd_load_iaa_device_defaults()
15 wq = idxd->wqs[0]; in idxd_load_iaa_device_defaults()
17 if (wq->state != IDXD_WQ_DISABLED) in idxd_load_iaa_device_defaults()
18 return -EPERM; in idxd_load_iaa_device_defaults()
21 set_bit(WQ_FLAG_DEDICATED, &wq->flags); in idxd_load_iaa_device_defaults()
22 wq->threshold = 0; in idxd_load_iaa_device_defaults()
25 wq->size = idxd->max_wq_size; in idxd_load_iaa_device_defaults()
28 wq->priority = 10; in idxd_load_iaa_device_defaults()
[all …]
/linux/drivers/ufs/core/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0+
5 # Copyright (C) 2011-2013 Samsung India Software Operations
30 bool "UFS Crypto Engine Support"
33 Enable Crypto Engine Support in UFS.
34 Enabling this makes it possible for the kernel to use the crypto
35 capabilities of the UFS device (if present) to perform crypto
/linux/drivers/crypto/ccp/
H A Dccp-crypto.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * AMD Cryptographic Coprocessor (CCP) crypto API support
16 #include <crypto/algapi.h>
17 #include <crypto/aes.h>
18 #include <crypto/internal/aead.h>
19 #include <crypto/aead.h>
20 #include <crypto/ctr.h>
21 #include <crypto/hash.h>
22 #include <crypto/sha1.h>
23 #include <crypto/sha2.h>
[all …]
/linux/drivers/mmc/core/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
10 This selects Hardware reset support aka pwrseq-emmc for eMMC
31 This selects simple hardware reset support aka pwrseq-simple for MMC
87 bool "MMC Crypto Engine Support"
90 Enable Crypto Engine Support in MMC.
91 Enabling this makes it possible for the kernel to use the crypto
92 capabilities of the MMC device (if present) to perform crypto
/linux/Documentation/devicetree/bindings/dma/
H A Dstericsson,dma40.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ST-Ericsson DMA40 DMA Engine
10 - Linus Walleij <linusw@kernel.org>
13 - $ref: dma-controller.yaml#
16 "#dma-cells":
32 10: Multi-Channel Display Engine MCDE RX
70 48: Crypto Accelerator 1
71 49: Crypto Accelerator 1 TX or Hash Accelerator 1 TX
[all …]
/linux/drivers/crypto/marvell/octeontx2/
H A Dotx2_cptvf_main.c1 // SPDX-License-Identifier: GPL-2.0-only
16 otx2_cpt_write64(cptvf->reg_base, BLKADDR_RVUM, 0, OTX2_RVU_VF_INT, in cptvf_enable_pfvf_mbox_intrs()
19 /* Enable PF-VF interrupt */ in cptvf_enable_pfvf_mbox_intrs()
20 otx2_cpt_write64(cptvf->reg_base, BLKADDR_RVUM, 0, in cptvf_enable_pfvf_mbox_intrs()
26 /* Disable PF-VF interrupt */ in cptvf_disable_pfvf_mbox_intrs()
27 otx2_cpt_write64(cptvf->reg_base, BLKADDR_RVUM, 0, in cptvf_disable_pfvf_mbox_intrs()
31 otx2_cpt_write64(cptvf->reg_base, BLKADDR_RVUM, 0, OTX2_RVU_VF_INT, in cptvf_disable_pfvf_mbox_intrs()
40 num_vec = pci_msix_vec_count(cptvf->pdev); in cptvf_register_interrupts()
42 return -EINVAL; in cptvf_register_interrupts()
44 /* Enable MSI-X */ in cptvf_register_interrupts()
[all …]
/linux/drivers/crypto/tegra/
H A Dtegra-se-main.c1 // SPDX-License-Identifier: GPL-2.0-only
2 // SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
4 * Crypto driver for NVIDIA Security Engine in Tegra Chips
8 #include <linux/dma-mapping.h>
13 #include <crypto/engine.h>
15 #include "tegra-se.h"
21 kref_get(&cmdbuf->ref); in tegra_se_cmdbuf_get()
30 dma_free_attrs(cmdbuf->dev, cmdbuf->size, cmdbuf->addr, in tegra_se_cmdbuf_release()
31 cmdbuf->iova, 0); in tegra_se_cmdbuf_release()
40 kref_put(&cmdbuf->ref, tegra_se_cmdbuf_release); in tegra_se_cmdbuf_put()
[all …]
/linux/drivers/crypto/intel/keembay/
H A Docs-hcu.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Intel Keem Bay OCS HCU Crypto Driver.
5 * Copyright (C) 2018-2020 Intel Corporation
8 #include <linux/dma-mapping.h>
28 * struct ocs_hcu_dev - OCS HCU device context.
32 * @engine: Crypto engine for the device.
41 struct crypto_engine *engine; member
48 * struct ocs_hcu_idata - Intermediate data generated by the HCU.
62 * struct ocs_hcu_hash_ctx - Context for OCS HCU hashing operation.
/linux/Documentation/crypto/
H A Dasync-tx-api.rst1 .. SPDX-License-Identifier: GPL-2.0
32 bulk memory transfers/transforms with support for inter-transactional
34 the details of different hardware offload engine implementations. Code
43 xor-parity-calculations of the md-raid5 driver using the offload engines
51 operation will be offloaded when an engine is available and carried out
54 operations to be submitted, like xor->copy->xor in the raid5 case. The
64 -----------------------------
72 ------------------------
92 -------------------------
94 The return value is non-NULL and points to a 'descriptor' when the operation
[all …]

12345