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/linux/drivers/crypto/aspeed/
H A DKconfig2 tristate "Support for Aspeed cryptographic engine driver"
6 Hash and Crypto Engine (HACE) is designed to accelerate the
13 bool "Enable Aspeed crypto debug messages"
16 Print Aspeed crypto debugging messages if you use this
22 bool "Enable Aspeed Hash & Crypto Engine (HACE) hash"
29 Select here to enable Aspeed Hash & Crypto Engine (HACE)
32 SHA-1, SHA-224, SHA-256, SHA-384, SHA-512, and so on.
35 bool "Enable Aspeed Hash & Crypto Engine (HACE) crypto"
43 Select here to enable Aspeed Hash & Crypto Engine (HACE)
44 crypto driver.
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/linux/Documentation/devicetree/bindings/firmware/
H A Dintel,ixp4xx-network-processing-engine.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/firmware/intel,ixp4xx-network-processing-engine.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Intel IXP4xx Network Processing Engine
11 - Linus Walleij <linus.walleij@linaro.org>
14 On the IXP4xx SoCs, the Network Processing Engine (NPE) is a small
16 and crypto tasks. It also manages the MDIO bus to the ethernet PHYs
24 - items:
25 - const: intel,ixp4xx-network-processing-engine
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/linux/drivers/crypto/allwinner/
H A DKconfig6 Say Y here to get to see options for Allwinner hardware crypto devices
19 Some Allwinner SoC have a crypto accelerator named
25 will be called sun4i-ss.
32 Select this option if you want to provide kernel-side support for
33 the Pseudo-Random Number Generator found in the Security System.
36 bool "Enable sun4i-ss stats"
40 Say y to enable sun4i-ss debug stats.
41 This will create /sys/kernel/debug/sun4i-ss/stats for displaying
45 tristate "Support for Allwinner Crypto Engine cryptographic offloader"
55 Select y here to have support for the crypto Engine available on
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/linux/Documentation/devicetree/bindings/crypto/
H A Dintel,ixp4xx-crypto.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/crypto/intel,ixp4xx-crypto.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Intel IXP4xx cryptographic engine
11 - Linus Walleij <linus.walleij@linaro.org>
14 The Intel IXP4xx cryptographic engine makes use of the IXP4xx NPE
15 (Network Processing Engine). Since it is not a device on its own
16 it is defined as a subnode of the NPE, if crypto support is
21 const: intel,ixp4xx-crypto
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H A Daspeed,ast2500-hace.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/crypto/aspeed,ast2500-hace.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ASPEED HACE hash and crypto Hardware Accelerator Engines
10 - Neal Liu <neal_liu@aspeedtech.com>
13 The Hash and Crypto Engine (HACE) is designed to accelerate the throughput
15 divided into two independently engines - Hash Engine and Crypto Engine.
20 - aspeed,ast2500-hace
21 - aspeed,ast2600-hace
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H A Dallwinner,sun4i-a10-crypto.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/crypto/allwinner,sun4i-a10-crypto.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
16 - const: allwinner,sun4i-a10-crypto
17 - items:
18 - const: allwinner,sun5i-a13-crypto
19 - const: allwinner,sun4i-a10-crypto
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H A Daspeed,ast2600-acry.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/crypto/aspeed,ast2600-acry.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Neal Liu <neal_liu@aspeedtech.com>
15 divided into two independent engines - ECC Engine and RSA Engine.
20 - aspeed,ast2600-acry
24 - description: acry base address & size
25 - description: acry sram base address & size
34 - compatible
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H A Dallwinner,sun8i-ce.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/crypto/allwinner,sun8i-ce.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner Crypto Engine driver
10 - Corentin Labbe <clabbe.montjoie@gmail.com>
15 - allwinner,sun8i-h3-crypto
16 - allwinner,sun8i-r40-crypto
17 - allwinner,sun20i-d1-crypto
18 - allwinner,sun50i-a64-crypto
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H A Dnvidia,tegra234-se-aes.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/crypto/nvidia,tegra234-se-aes.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra Security Engine for AES algorithms
10 The Tegra Security Engine accelerates the following AES encryption/decryption
11 algorithms - AES-ECB, AES-CBC, AES-OFB, AES-XTS, AES-CTR, AES-GCM, AES-CCM,
12 AES-CMAC
15 - Akhil R <akhilrajeev@nvidia.com>
19 const: nvidia,tegra234-se-aes
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H A Dnvidia,tegra234-se-hash.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/crypto/nvidia,tegra234-se-hash.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra Security Engine for HASH algorithms
10 The Tegra Security HASH Engine accelerates the following HASH functions -
11 SHA1, SHA224, SHA256, SHA384, SHA512, SHA3-224, SHA3-256, SHA3-384, SHA3-512
15 - Akhil R <akhilrajeev@nvidia.com>
19 const: nvidia,tegra234-se-hash
30 dma-coherent: true
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H A Damlogic,gxl-crypto.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/crypto/amlogic,gxl-crypto.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Corentin Labbe <clabbe@baylibre.com>
15 - const: amlogic,gxl-crypto
22 - description: Interrupt for flow 0
23 - description: Interrupt for flow 1
28 clock-names:
32 - compatible
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/linux/drivers/soc/qcom/
H A Dice.c1 // SPDX-License-Identifier: GPL-2.0
3 * Qualcomm ICE (Inline Crypto Engine) support.
5 * Copyright (c) 2013-2019, The Linux Foundation. All rights reserved.
82 #define qcom_ice_writel(engine, val, reg) \ argument
83 writel((val), (engine)->base + (reg))
85 #define qcom_ice_readl(engine, reg) \ argument
86 readl((engine)->base + (reg))
105 struct device *dev = ice->dev; in qcom_ice_check_supported()
117 dev_info(dev, "Found QC Inline Crypto Engine (ICE) v%d.%d.%d\n", in qcom_ice_check_supported()
140 * ICE-capable storage driver(s) need to know early on whether to in qcom_ice_check_supported()
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/linux/drivers/crypto/
H A Dsa2ul.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * K3 SA2UL crypto accelerator driver
5 * Copyright (C) 2018-2020 Texas Instruments Incorporated - http://www.ti.com
15 #include <crypto/aes.h>
16 #include <crypto/sha1.h>
17 #include <crypto/sha2.h>
35 * Encoding used to identify the typo of crypto operation
62 ((ctx_sz) ? ((ctx_sz) / 32 - 1) : 0)
70 /* Next Engine Select code in CP_ACE */
71 #define SA_ENG_ID_EM1 2 /* Enc/Dec engine with AES/DEC core */
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/linux/drivers/crypto/amlogic/
H A Damlogic-gxl.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * amlogic.h - hardware cryptographic offloader for Amlogic SoC
5 * Copyright (C) 2018-2019 Corentin LABBE <clabbe@baylibre.com>
7 #include <crypto/aes.h>
8 #include <crypto/engine.h>
9 #include <crypto/skcipher.h>
11 #include <linux/crypto.h>
34 * struct meson_desc - Descriptor for DMA operations
40 * @len: 0-16 length of data to operate
44 * @mode: 20-23 Type of algorithm (AES, SHA)
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/linux/drivers/crypto/hisilicon/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
4 tristate "Support for Hisilicon SEC crypto block cipher accelerator"
12 Support for Hisilicon SEC Engine in Hip06 and Hip07
18 tristate "Support for HiSilicon SEC2 crypto block cipher accelerator"
35 Support for HiSilicon SEC Engine of version 2 in crypto subsystem.
50 interface. Specific engine driver may use this module.
74 Support for HiSilicon HPRE(High Performance RSA Engine)
/linux/Documentation/arch/powerpc/
H A Dvas-api.rst1 .. SPDX-License-Identifier: GPL-2.0
2 .. _VAS-API:
12 allows both userspace and kernel communicate to co-processor
14 unit comprises of one or more hardware engines or co-processor types
16 userspace applications will have access to only GZIP Compression engine
21 Requests to the GZIP engine must be formatted as a co-processor Request
24 the engine's request queue.
26 The GZIP engine provides two priority levels of requests: Normal and
37 Application access to the GZIP engine is provided through
38 /dev/crypto/nx-gzip device node implemented by the VAS/NX device driver.
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/linux/drivers/crypto/allwinner/sun8i-ss/
H A Dsun8i-ss.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * sun8i-ss.h - hardware cryptographic offloader for
6 * Copyright (C) 2016-2019 Corentin LABBE <clabbe.montjoie@gmail.com>
8 #include <crypto/aes.h>
9 #include <crypto/des.h>
10 #include <crypto/engine.h>
11 #include <crypto/rng.h>
12 #include <crypto/skcipher.h>
15 #include <linux/crypto.h>
16 #include <crypto/internal/hash.h>
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/linux/drivers/crypto/gemini/
H A Dsl3516-ce.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * sl3516-ce.h - hardware cryptographic offloader for cortina/gemini SoC
8 * Called either Crypto Acceleration Engine Module, Security Acceleration Engine
9 * or IPSEC module in the datasheet, it will be called Crypto Engine for short
16 #include <crypto/aes.h>
17 #include <crypto/engine.h>
18 #include <crypto/scatterwalk.h>
19 #include <crypto/skcipher.h>
90 * struct sl3516_ce_descriptor - descriptor for CE operations
100 * struct desc_frame_ctrl - Information for the current descriptor
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/linux/drivers/dma/idxd/
H A Ddefaults.c1 // SPDX-License-Identifier: GPL-2.0
8 struct idxd_engine *engine; in idxd_load_iaa_device_defaults() local
12 if (!test_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags)) in idxd_load_iaa_device_defaults()
15 wq = idxd->wqs[0]; in idxd_load_iaa_device_defaults()
17 if (wq->state != IDXD_WQ_DISABLED) in idxd_load_iaa_device_defaults()
18 return -EPERM; in idxd_load_iaa_device_defaults()
21 set_bit(WQ_FLAG_DEDICATED, &wq->flags); in idxd_load_iaa_device_defaults()
22 wq->threshold = 0; in idxd_load_iaa_device_defaults()
25 wq->size = idxd->max_wq_size; in idxd_load_iaa_device_defaults()
28 wq->priority = 10; in idxd_load_iaa_device_defaults()
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/linux/drivers/crypto/starfive/
H A DKconfig2 # StarFive crypto drivers configuration
6 tristate "StarFive JH7110 cryptographic engine driver"
22 Support for StarFive JH7110 crypto hardware acceleration engine.
26 If you choose 'M' here, this module will be called jh7110-crypto.
/linux/drivers/ufs/core/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0+
5 # Copyright (C) 2011-2013 Samsung India Software Operations
30 bool "UFS Crypto Engine Support"
33 Enable Crypto Engine Support in UFS.
34 Enabling this makes it possible for the kernel to use the crypto
35 capabilities of the UFS device (if present) to perform crypto
/linux/drivers/crypto/ccp/
H A Dccp-crypto.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * AMD Cryptographic Coprocessor (CCP) crypto API support
16 #include <crypto/algapi.h>
17 #include <crypto/aes.h>
18 #include <crypto/internal/aead.h>
19 #include <crypto/aead.h>
20 #include <crypto/ctr.h>
21 #include <crypto/hash.h>
22 #include <crypto/sha1.h>
23 #include <crypto/sha2.h>
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/linux/drivers/mmc/core/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
10 This selects Hardware reset support aka pwrseq-emmc for eMMC
31 This selects simple hardware reset support aka pwrseq-simple for MMC
87 bool "MMC Crypto Engine Support"
90 Enable Crypto Engine Support in MMC.
91 Enabling this makes it possible for the kernel to use the crypto
92 capabilities of the MMC device (if present) to perform crypto
/linux/Documentation/devicetree/bindings/dma/
H A Dstericsson,dma40.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ST-Ericsson DMA40 DMA Engine
10 - Linus Walleij <linus.walleij@linaro.org>
13 - $ref: dma-controller.yaml#
16 "#dma-cells":
32 10: Multi-Channel Display Engine MCDE RX
70 48: Crypto Accelerator 1
71 49: Crypto Accelerator 1 TX or Hash Accelerator 1 TX
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/linux/drivers/crypto/intel/keembay/
H A Docs-hcu.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Intel Keem Bay OCS HCU Crypto Driver.
5 * Copyright (C) 2018-2020 Intel Corporation
8 #include <linux/dma-mapping.h>
28 * struct ocs_hcu_dev - OCS HCU device context.
32 * @engine: Crypto engine for the device.
41 struct crypto_engine *engine; member
48 * struct ocs_hcu_idata - Intermediate data generated by the HCU.
62 * struct ocs_hcu_hash_ctx - Context for OCS HCU hashing operation.

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