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/linux/arch/arm64/boot/dts/rockchip/
H A Drk3588-base.dtsi6 #include <dt-bindings/clock/rockchip,rk3588-cru.h>
11 #include <dt-bindings/reset/rockchip,rk3588-cru.h>
455 clocks = <&cru CLK_GPU>, <&cru CLK_GPU_COREGROUP>,
456 <&cru CLK_GPU_STACKS>;
471 clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>,
472 <&cru ACLK_USB3OTG0>;
479 resets = <&cru SRST_A_USB3OTG0>;
493 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>;
504 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>;
515 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>;
[all …]
H A Drk3576.dtsi6 #include <dt-bindings/clock/rockchip,rk3576-cru.h>
12 #include <dt-bindings/reset/rockchip,rk3576-cru.h>
437 clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>;
449 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
461 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
473 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
485 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
676 clocks = <&cru ACLK_PCIE0_MST>, <&cru ACLK_PCIE0_SLV>,
677 <&cru ACLK_PCIE0_DBI>, <&cru PCLK_PCIE0>,
678 <&cru CLK_PCIE0_AUX>;
[all …]
H A Drk3528.dtsi12 #include <dt-bindings/clock/rockchip,rk3528-cru.h>
14 #include <dt-bindings/reset/rockchip,rk3528-cru.h>
179 clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>;
191 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
204 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
217 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
230 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
294 clocks = <&cru ACLK_PCIE>, <&cru HCLK_PCIE_SLV>,
295 <&cru HCLK_PCIE_DBI>, <&cru PCLK_PCIE>,
296 <&cru CLK_PCIE_AUX>;
[all …]
H A Drk3399-base.dtsi6 #include <dt-bindings/clock/rk3399-cru.h>
85 clocks = <&cru ARMCLKL>;
104 clocks = <&cru ARMCLKL>;
123 clocks = <&cru ARMCLKL>;
142 clocks = <&cru ARMCLKL>;
161 clocks = <&cru ARMCLKB>;
186 clocks = <&cru ARMCLKB>;
255 clocks = <&cru SCLK_DDRC>;
302 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
303 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
[all …]
H A Drk3562.dtsi6 #include <dt-bindings/clock/rockchip,rk3562-cru.h>
12 #include <dt-bindings/reset/rockchip,rk3562-cru.h>
232 clocks = <&cru PCLK_PMU0_GPIO0>, <&cru DBCLK_PMU0_GPIO0>;
244 clocks = <&cru PCLK_PERI_GPIO1>, <&cru DCLK_PERI_GPIO1>;
256 clocks = <&cru PCLK_PERI_GPIO2>, <&cru DCLK_PERI_GPIO2>;
268 clocks = <&cru PCLK_GPIO3_VCCIO156>, <&cru DCLK_BUS_GPIO3>;
280 clocks = <&cru PCLK_GPIO4_VCCIO156>, <&cru DCLK_BUS_GPIO4>;
328 clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>,
329 <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>,
330 <&cru CLK_PCIE20_AUX>;
[all …]
H A Drk3328.dtsi6 #include <dt-bindings/clock/rk3328-cru.h>
44 clocks = <&cru ARMCLK>;
63 clocks = <&cru ARMCLK>;
82 clocks = <&cru ARMCLK>;
101 clocks = <&cru ARMCLK>;
246 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
258 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
270 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
282 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
295 clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>;
[all …]
H A Dpx30.dtsi6 #include <dt-bindings/clock/px30-cru.h>
46 clocks = <&cru ARMCLK>;
58 clocks = <&cru ARMCLK>;
70 clocks = <&cru ARMCLK>;
82 clocks = <&cru ARMCLK>;
269 clocks = <&cru HCLK_HOST>,
270 <&cru HCLK_OTG>,
271 <&cru SCLK_OTG_ADP>;
277 clocks = <&cru HCLK_SDMMC>,
278 <&cru SCLK_SDMMC>;
[all …]
H A Drk3308.dtsi7 #include <dt-bindings/clock/rk3308-cru.h>
51 clocks = <&cru ARMCLK>;
201 assigned-clocks = <&cru USB480M>;
203 clocks = <&cru SCLK_USBPHY_REF>;
245 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
258 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
271 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
284 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
297 clocks = <&cru PCLK_WDT>;
306 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
[all …]
/linux/arch/arm/boot/dts/rockchip/
H A Drv1126.dtsi6 #include <dt-bindings/clock/rockchip,rv1126-cru.h>
43 clocks = <&cru ARMCLK>;
51 clocks = <&cru ARMCLK>;
59 clocks = <&cru ARMCLK>;
67 clocks = <&cru ARMCLK>;
186 clocks = <&cru HCLK_EMMC>,
187 <&cru CLK_EMMC>,
188 <&cru HCLK_NANDC>,
189 <&cru CLK_NANDC>,
190 <&cru HCLK_SFC>,
[all …]
H A Drk322x.dtsi7 #include <dt-bindings/clock/rk3228-cru.h>
36 resets = <&cru SRST_CORE0>;
39 clocks = <&cru ARMCLK>;
47 resets = <&cru SRST_CORE1>;
57 resets = <&cru SRST_CORE2>;
67 resets = <&cru SRST_CORE3>;
143 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
156 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
166 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
180 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
[all …]
H A Drk3128.dtsi6 #include <dt-bindings/clock/rk3128-cru.h>
51 clocks = <&cru ARMCLK>;
52 resets = <&cru SRST_CORE0>;
61 resets = <&cru SRST_CORE1>;
69 resets = <&cru SRST_CORE2>;
77 resets = <&cru SRST_CORE3>;
196 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
199 resets = <&cru SRST_GPU>;
216 clocks = <&cru ACLK_CIF>,
217 <&cru HCLK_CIF>,
[all …]
H A Drk3066a.dtsi9 #include <dt-bindings/clock/rk3066a-cru.h>
41 clocks = <&cru ARMCLK>;
89 clocks = <&cru ACLK_LCDC0>,
90 <&cru DCLK_LCDC0>,
91 <&cru HCLK_LCDC0>;
94 resets = <&cru SRST_LCDC0_AXI>,
95 <&cru SRST_LCDC0_AHB>,
96 <&cru SRST_LCDC0_DCLK>;
115 clocks = <&cru ACLK_LCDC1>,
116 <&cru DCLK_LCDC1>,
[all …]
H A Drk3xxx.dtsi46 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
48 assigned-clocks = <&cru ACLK_GPU>;
50 resets = <&cru SRST_GPU>;
60 clocks = <&cru ACLK_VDPU>, <&cru HCLK_VDPU>,
61 <&cru ACLK_VEPU>, <&cru HCLK_VEPU>;
82 clocks = <&cru CORE_PERI>;
96 clocks = <&cru CORE_PERI>;
114 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
125 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
173 clocks = <&cru HCLK_OTG0>;
[all …]
H A Drv1108.dtsi6 #include <dt-bindings/clock/rv1108-cru.h>
35 clocks = <&cru ARMCLK>;
102 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
117 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
132 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
146 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
160 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
174 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
186 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
198 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
[all …]
H A Drk3188.dtsi9 #include <dt-bindings/clock/rk3188-cru.h>
26 clocks = <&cru ARMCLK>;
28 resets = <&cru SRST_CORE0>;
36 resets = <&cru SRST_CORE1>;
44 resets = <&cru SRST_CORE2>;
52 resets = <&cru SRST_CORE3>;
118 clocks = <&cru ACLK_LCDC0>, <&cru DCLK_LCDC0>, <&cru HCLK_LCDC0>;
121 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
135 clocks = <&cru ACLK_LCDC1>, <&cru DCLK_LCDC1>, <&cru HCLK_LCDC1>;
138 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
[all …]
/linux/include/dt-bindings/reset/
H A Drockchip,rk3506-cru.h10 /* CRU-->SOFTRST_CON00 */
21 /* CRU-->SOFTRST_CON02 */
26 /* CRU-->SOFTRST_CON03 */
35 /* CRU-->SOFTRST_CON04 */
46 /* CRU-->SOFTRST_CON05 */
58 /* CRU-->SOFTRST_CON06 */
76 /* CRU-->SOFTRST_CON07 */
91 /* CRU-->SOFTRST_CON08 */
95 /* CRU-->SOFTRST_CON09 */
99 /* CRU-->SOFTRST_CON10 */
[all …]
/linux/Documentation/devicetree/bindings/pci/
H A Drockchip,rk3399-pcie-ep.yaml42 #include <dt-bindings/clock/rk3399-cru.h>
52 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
53 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
58 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
59 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE> ,
60 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, <&cru SRST_A_PCIE>;
H A Drockchip-dw-pcie-ep.yaml51 #include <dt-bindings/clock/rockchip,rk3588-cru.h>
55 #include <dt-bindings/reset/rockchip,rk3588-cru.h>
69 clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>,
70 <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>,
71 <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>;
91 resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>;
/linux/drivers/clk/rockchip/
H A Drst-rk3506.c9 #include <dt-bindings/reset/rockchip,rk3506-cru.h>
17 /* CRU-->SOFTRST_CON00 */
28 /* CRU-->SOFTRST_CON02 */
33 /* CRU-->SOFTRST_CON03 */
42 /* CRU-->SOFTRST_CON04 */
53 /* CRU-->SOFTRST_CON05 */
65 /* CRU-->SOFTRST_CON06 */
83 /* CRU-->SOFTRST_CON07 */
98 /* CRU-->SOFTRST_CON08 */
102 /* CRU-->SOFTRST_CON09 */
[all …]
/linux/Documentation/devicetree/bindings/usb/
H A Drockchip,rk3399-dwc3.yaml73 #include <dt-bindings/clock/rk3399-cru.h>
86 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
87 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
88 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
92 resets = <&cru SRST_A_USB3_OTG0>;
99 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru ACLK_USB3OTG0>,
100 <&cru SCLK_USB3OTG0_SUSPEND>;
/linux/Documentation/devicetree/bindings/clock/
H A Drockchip,px30-cru.yaml4 $id: http://devicetree.org/schemas/clock/rockchip,px30-cru.yaml#
7 title: Rockchip PX30 Clock and Reset Unit (CRU)
19 preprocessor macros in the dt-bindings/clock/px30-cru.h headers and can be
33 - rockchip,px30-cru
48 - description: Clock for both PMUCRU and CRU
49 - description: Clock for CRU (sourced from PMUCRU)
77 const: rockchip,px30-cru
99 #include <dt-bindings/clock/px30-cru.h>
111 cru: clock-controller@ff2b0000 {
112 compatible = "rockchip,px30-cru";
H A Drockchip,rk3188-cru.yaml4 $id: http://devicetree.org/schemas/clock/rockchip,rk3188-cru.yaml#
7 title: Rockchip RK3188/RK3066 Clock and Reset Unit (CRU)
19 preprocessor macros in the dt-bindings/clock/rk3188-cru.h and
20 dt-bindings/clock/rk3066-cru.h headers and can be used in device tree sources.
36 - rockchip,rk3066a-cru
37 - rockchip,rk3188-cru
38 - rockchip,rk3188a-cru
72 cru: clock-controller@20000000 {
73 compatible = "rockchip,rk3188-cru";
/linux/Documentation/devicetree/bindings/ufs/
H A Drockchip,rk3576-ufshc.yaml76 #include <dt-bindings/clock/rockchip,rk3576-cru.h>
77 #include <dt-bindings/reset/rockchip,rk3576-cru.h>
95 clocks = <&cru ACLK_UFS_SYS>, <&cru PCLK_USB_ROOT>, <&cru PCLK_MPHY>,
96 <&cru CLK_REF_UFS_CLKOUT>;
100 resets = <&cru SRST_A_UFS_BIU>, <&cru SRST_A_UFS_SYS>, <&cru SRST_A_UFS>,
101 <&cru SRST_P_UFS_GRF>;
/linux/Documentation/devicetree/bindings/display/rockchip/
H A Drockchip,rk3399-cdn-dp.yaml121 #include <dt-bindings/clock/rk3399-cru.h>
131 assigned-clocks = <&cru SCLK_DP_CORE>;
134 clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>, <&cru SCLK_SPDIF_REC_DPTX>,
135 <&cru PCLK_VIO_GRF>;
139 resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>,
140 <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>;
/linux/Documentation/devicetree/bindings/phy/
H A Dphy-rockchip-usbdp.yaml130 #include <dt-bindings/clock/rockchip,rk3588-cru.h>
131 #include <dt-bindings/reset/rockchip,rk3588-cru.h>
137 clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
138 <&cru CLK_USBDP_PHY0_IMMORTAL>,
139 <&cru PCLK_USBDPPHY0>,
142 resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>,
143 <&cru SRST_USBDP_COMBO_PHY0_CMN>,
144 <&cru SRST_USBDP_COMBO_PHY0_LANE>,
145 <&cru SRST_USBDP_COMBO_PHY0_PCS>,
146 <&cru SRST_P_USBDPPHY0>;

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