/linux/arch/arm64/boot/dts/rockchip/ |
H A D | rk356x-base.dtsi | 6 #include <dt-bindings/clock/rk3568-cru.h> 217 clocks = <&cru ACLK_SATA1>, <&cru CLK_SATA1_PMALIVE>, 218 <&cru CLK_SATA1_RXOOB>; 231 clocks = <&cru ACLK_SATA2>, <&cru CLK_SATA2_PMALIVE>, 232 <&cru CLK_SATA2_RXOOB>; 246 clocks = <&cru CLK_USB3OTG0_REF>, <&cru CLK_USB3OTG0_SUSPEND>, 247 <&cru ACLK_USB3OTG0>; 253 resets = <&cru SRST_USB3OTG0>; 262 clocks = <&cru CLK_USB3OTG1_REF>, <&cru CLK_USB3OTG1_SUSPEND>, 263 <&cru ACLK_USB3OTG1>; [all …]
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H A D | rk3399-base.dtsi | 6 #include <dt-bindings/clock/rk3399-cru.h> 85 clocks = <&cru ARMCLKL>; 104 clocks = <&cru ARMCLKL>; 123 clocks = <&cru ARMCLKL>; 142 clocks = <&cru ARMCLKL>; 161 clocks = <&cru ARMCLKB>; 186 clocks = <&cru ARMCLKB>; 255 clocks = <&cru SCLK_DDRC>; 302 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>, 303 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>; [all …]
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H A D | rk3562.dtsi | 6 #include <dt-bindings/clock/rockchip,rk3562-cru.h> 12 #include <dt-bindings/reset/rockchip,rk3562-cru.h> 232 clocks = <&cru PCLK_PMU0_GPIO0>, <&cru DBCLK_PMU0_GPIO0>; 244 clocks = <&cru PCLK_PERI_GPIO1>, <&cru DCLK_PERI_GPIO1>; 256 clocks = <&cru PCLK_PERI_GPIO2>, <&cru DCLK_PERI_GPIO2>; 268 clocks = <&cru PCLK_GPIO3_VCCIO156>, <&cru DCLK_BUS_GPIO3>; 280 clocks = <&cru PCLK_GPIO4_VCCIO156>, <&cru DCLK_BUS_GPIO4>; 328 clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>, 329 <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>, 330 <&cru CLK_PCIE20_AUX>; [all …]
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H A D | rk3368.dtsi | 6 #include <dt-bindings/clock/rk3368-cru.h> 186 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 187 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 191 resets = <&cru SRST_MMC0>; 200 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>, 201 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>; 205 resets = <&cru SRST_SDIO0>; 214 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 215 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 219 resets = <&cru SRST_EMMC>; [all …]
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H A D | px30.dtsi | 6 #include <dt-bindings/clock/px30-cru.h> 46 clocks = <&cru ARMCLK>; 58 clocks = <&cru ARMCLK>; 70 clocks = <&cru ARMCLK>; 82 clocks = <&cru ARMCLK>; 269 clocks = <&cru HCLK_HOST>, 270 <&cru HCLK_OTG>, 271 <&cru SCLK_OTG_ADP>; 277 clocks = <&cru HCLK_SDMMC>, 278 <&cru SCLK_SDMMC>; [all …]
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H A D | rk3568.dtsi | 102 clocks = <&cru ACLK_SATA0>, <&cru CLK_SATA0_PMALIVE>, 103 <&cru CLK_SATA0_RXOOB>; 143 <&cru PCLK_PCIE30PHY>; 145 resets = <&cru SRST_PCIE30PHY>; 156 clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>, 157 <&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>, 158 <&cru CLK_PCIE30X1_AUX_NDFT>; 190 resets = <&cru SRST_PCIE30X1_POWERUP>; 209 clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>, 210 <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>, [all …]
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H A D | rk3308.dtsi | 7 #include <dt-bindings/clock/rk3308-cru.h> 51 clocks = <&cru ARMCLK>; 201 assigned-clocks = <&cru USB480M>; 203 clocks = <&cru SCLK_USBPHY_REF>; 245 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; 258 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 271 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 284 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 297 clocks = <&cru PCLK_WDT>; 306 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; [all …]
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/linux/arch/arm/boot/dts/rockchip/ |
H A D | rv1126.dtsi | 6 #include <dt-bindings/clock/rockchip,rv1126-cru.h> 43 clocks = <&cru ARMCLK>; 51 clocks = <&cru ARMCLK>; 59 clocks = <&cru ARMCLK>; 67 clocks = <&cru ARMCLK>; 186 clocks = <&cru HCLK_EMMC>, 187 <&cru CLK_EMMC>, 188 <&cru HCLK_NANDC>, 189 <&cru CLK_NANDC>, 190 <&cru HCLK_SFC>, [all …]
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H A D | rk322x.dtsi | 7 #include <dt-bindings/clock/rk3228-cru.h> 36 resets = <&cru SRST_CORE0>; 39 clocks = <&cru ARMCLK>; 47 resets = <&cru SRST_CORE1>; 57 resets = <&cru SRST_CORE2>; 67 resets = <&cru SRST_CORE3>; 143 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>; 156 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>; 166 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>; 180 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>; [all …]
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H A D | rk3288.dtsi | 7 #include <dt-bindings/clock/rk3288-cru.h> 70 resets = <&cru SRST_CORE0>; 73 clocks = <&cru ARMCLK>; 80 resets = <&cru SRST_CORE1>; 83 clocks = <&cru ARMCLK>; 90 resets = <&cru SRST_CORE2>; 93 clocks = <&cru ARMCLK>; 100 resets = <&cru SRST_CORE3>; 103 clocks = <&cru ARMCLK>; 205 clocks = <&cru PCLK_TIMER>, <&xin24m>; [all …]
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H A D | rk3128.dtsi | 6 #include <dt-bindings/clock/rk3128-cru.h> 51 clocks = <&cru ARMCLK>; 52 resets = <&cru SRST_CORE0>; 61 resets = <&cru SRST_CORE1>; 69 resets = <&cru SRST_CORE2>; 77 resets = <&cru SRST_CORE3>; 196 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; 199 resets = <&cru SRST_GPU>; 216 clocks = <&cru ACLK_CIF>, 217 <&cru HCLK_CIF>, [all …]
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H A D | rk3xxx.dtsi | 46 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; 48 assigned-clocks = <&cru ACLK_GPU>; 50 resets = <&cru SRST_GPU>; 60 clocks = <&cru ACLK_VDPU>, <&cru HCLK_VDPU>, 61 <&cru ACLK_VEPU>, <&cru HCLK_VEPU>; 82 clocks = <&cru CORE_PERI>; 96 clocks = <&cru CORE_PERI>; 114 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 125 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 173 clocks = <&cru HCLK_OTG0>; [all …]
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H A D | rk3066a.dtsi | 9 #include <dt-bindings/clock/rk3066a-cru.h> 41 clocks = <&cru ARMCLK>; 89 clocks = <&cru ACLK_LCDC0>, 90 <&cru DCLK_LCDC0>, 91 <&cru HCLK_LCDC0>; 94 resets = <&cru SRST_LCDC0_AXI>, 95 <&cru SRST_LCDC0_AHB>, 96 <&cru SRST_LCDC0_DCLK>; 115 clocks = <&cru ACLK_LCDC1>, 116 <&cru DCLK_LCDC1>, [all …]
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H A D | rk3036.dtsi | 7 #include <dt-bindings/clock/rk3036-cru.h> 44 resets = <&cru SRST_CORE0>; 50 clocks = <&cru ARMCLK>; 57 resets = <&cru SRST_CORE1>; 114 assigned-clocks = <&cru SCLK_GPU>; 116 clocks = <&cru SCLK_GPU>, <&cru SCLK_GPU>; 119 resets = <&cru SRST_GPU>; 128 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; 138 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; 148 clocks = <&cru ACLK_LCDC>, <&cru SCLK_LCDC>, <&cru HCLK_LCDC>; [all …]
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H A D | rv1108.dtsi | 6 #include <dt-bindings/clock/rv1108-cru.h> 35 clocks = <&cru ARMCLK>; 102 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 117 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 132 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 146 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 160 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 174 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 186 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>; 198 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; [all …]
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H A D | rk3188.dtsi | 9 #include <dt-bindings/clock/rk3188-cru.h> 26 clocks = <&cru ARMCLK>; 28 resets = <&cru SRST_CORE0>; 36 resets = <&cru SRST_CORE1>; 44 resets = <&cru SRST_CORE2>; 52 resets = <&cru SRST_CORE3>; 118 clocks = <&cru ACLK_LCDC0>, <&cru DCLK_LCDC0>, <&cru HCLK_LCDC0>; 121 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>; 135 clocks = <&cru ACLK_LCDC1>, <&cru DCLK_LCDC1>, <&cru HCLK_LCDC1>; 138 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>; [all …]
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/linux/Documentation/devicetree/bindings/pci/ |
H A D | rockchip,rk3399-pcie-ep.yaml | 42 #include <dt-bindings/clock/rk3399-cru.h> 52 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>, 53 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>; 58 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>, 59 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE> , 60 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, <&cru SRST_A_PCIE>;
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H A D | rockchip-dw-pcie-ep.yaml | 51 #include <dt-bindings/clock/rockchip,rk3588-cru.h> 55 #include <dt-bindings/reset/rockchip,rk3588-cru.h> 69 clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>, 70 <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>, 71 <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>; 91 resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>;
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/linux/Documentation/devicetree/bindings/usb/ |
H A D | rockchip,rk3399-dwc3.yaml | 73 #include <dt-bindings/clock/rk3399-cru.h> 86 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>, 87 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>, 88 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>; 92 resets = <&cru SRST_A_USB3_OTG0>; 99 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru ACLK_USB3OTG0>, 100 <&cru SCLK_USB3OTG0_SUSPEND>;
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/linux/Documentation/devicetree/bindings/clock/ |
H A D | rockchip,px30-cru.yaml | 4 $id: http://devicetree.org/schemas/clock/rockchip,px30-cru.yaml# 7 title: Rockchip PX30 Clock and Reset Unit (CRU) 19 preprocessor macros in the dt-bindings/clock/px30-cru.h headers and can be 33 - rockchip,px30-cru 48 - description: Clock for both PMUCRU and CRU 49 - description: Clock for CRU (sourced from PMUCRU) 77 const: rockchip,px30-cru 99 #include <dt-bindings/clock/px30-cru.h> 111 cru: clock-controller@ff2b0000 { 112 compatible = "rockchip,px30-cru";
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H A D | rockchip,rk3188-cru.yaml | 4 $id: http://devicetree.org/schemas/clock/rockchip,rk3188-cru.yaml# 7 title: Rockchip RK3188/RK3066 Clock and Reset Unit (CRU) 19 preprocessor macros in the dt-bindings/clock/rk3188-cru.h and 20 dt-bindings/clock/rk3066-cru.h headers and can be used in device tree sources. 36 - rockchip,rk3066a-cru 37 - rockchip,rk3188-cru 38 - rockchip,rk3188a-cru 72 cru: clock-controller@20000000 { 73 compatible = "rockchip,rk3188-cru";
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H A D | rockchip,rk3128-cru.yaml | 4 $id: http://devicetree.org/schemas/clock/rockchip,rk3128-cru.yaml# 7 title: Rockchip RK3126/RK3128 Clock and Reset Unit (CRU) 19 preprocessor macros in the dt-bindings/clock/rk3128-cru.h headers and can be 26 - rockchip,rk3126-cru 27 - rockchip,rk3128-cru 70 cru: clock-controller@20000000 { 71 compatible = "rockchip,rk3128-cru";
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/linux/Documentation/devicetree/bindings/ufs/ |
H A D | rockchip,rk3576-ufshc.yaml | 76 #include <dt-bindings/clock/rockchip,rk3576-cru.h> 77 #include <dt-bindings/reset/rockchip,rk3576-cru.h> 95 clocks = <&cru ACLK_UFS_SYS>, <&cru PCLK_USB_ROOT>, <&cru PCLK_MPHY>, 96 <&cru CLK_REF_UFS_CLKOUT>; 100 resets = <&cru SRST_A_UFS_BIU>, <&cru SRST_A_UFS_SYS>, <&cru SRST_A_UFS>, 101 <&cru SRST_P_UFS_GRF>;
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/linux/Documentation/devicetree/bindings/display/rockchip/ |
H A D | rockchip,rk3399-cdn-dp.yaml | 121 #include <dt-bindings/clock/rk3399-cru.h> 131 assigned-clocks = <&cru SCLK_DP_CORE>; 134 clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>, <&cru SCLK_SPDIF_REC_DPTX>, 135 <&cru PCLK_VIO_GRF>; 139 resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>, 140 <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>;
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/linux/Documentation/devicetree/bindings/phy/ |
H A D | phy-rockchip-usbdp.yaml | 130 #include <dt-bindings/clock/rockchip,rk3588-cru.h> 131 #include <dt-bindings/reset/rockchip,rk3588-cru.h> 137 clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>, 138 <&cru CLK_USBDP_PHY0_IMMORTAL>, 139 <&cru PCLK_USBDPPHY0>, 142 resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>, 143 <&cru SRST_USBDP_COMBO_PHY0_CMN>, 144 <&cru SRST_USBDP_COMBO_PHY0_LANE>, 145 <&cru SRST_USBDP_COMBO_PHY0_PCS>, 146 <&cru SRST_P_USBDPPHY0>;
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