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/linux/Documentation/devicetree/bindings/opp/
H A Dopp-v2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/opp/opp-v2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Viresh Kumar <viresh.kumar@linaro.org>
13 - $ref: opp-v2-base.yaml#
17 const: operating-points-v2
22 - |
24 * Example 1: Single cluster Dual-core ARM cortex A9, switch DVFS states
28 #address-cells = <1>;
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dmsm8996-oneplus-common.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
12 #include <dt-bindings/sound/qcom,q6afe.h>
13 #include <dt-bindings/sound/qcom,q6asm.h>
14 #include <dt-bindings/sound/qcom,wcd9335.h>
23 compatible = "simple-battery";
25 constant-charge-current-max-microamp = <3000000>;
26 voltage-min-design-microvolt = <3400000>;
30 stdout-path = "serial1:115200n8";
[all …]
H A Dsdm845-oneplus-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 /dts-v1/;
10 #include <dt-bindings/input/linux-event-codes.h>
11 #include <dt-bindings/leds/common.h>
12 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
13 #include <dt-bindings/sound/qcom,q6afe.h>
14 #include <dt-bindings/sound/qcom,q6asm.h>
17 #include "sdm845-wcd9340.dtsi"
21 /delete-node/ &rmtfs_mem;
30 stdout-path = "serial0:115200n8";
[all …]
/linux/Documentation/devicetree/bindings/cpufreq/
H A Dcpufreq-mediatek.txt5 - clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock names.
6 - clock-names: Should contain the following:
7 "cpu" - The multiplexer for clock input of CPU cluster.
8 "intermediate" - A parent of "cpu" clock which is used as "intermediate" clock
9 source (usually MAINPLL) when the original CPU PLL is under
11 Please refer to Documentation/devicetree/bindings/clock/clock-bindings.txt for
13 - operating-points-v2: Please refer to Documentation/devicetree/bindings/opp/opp-v2.yaml
15 - proc-supply: Regulator for Vproc of CPU cluster.
18 - sram-supply: Regulator for Vsram of CPU cluster. When present, the cpufreq driver
23 - mediatek,cci:
[all …]
/linux/arch/arm/boot/dts/nvidia/
H A Dtegra30-cardhu.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/input/input.h>
3 #include <dt-bindings/thermal/thermal.h>
5 #include "tegra30-cpu-opp.dtsi"
6 #include "tegra30-cpu-opp-microvolt.dtsi"
16 * use tegra30-cardhu-a02.dts, Cardhu fab version A04 and later, use
17 * tegra30-cardhu-a04.dts.
20 * The sticker will have number like 600-81291-1000-002 C.3. In this 4th
22 * The (downstream internal) U-Boot of Cardhu display the board-id as
43 stdout-path = "serial0:115200n8";
[all …]
/linux/arch/arm64/boot/dts/amlogic/
H A Dmeson-g12b-khadas-vim3.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 vddcpu_a: regulator-vddcpu-a {
15 compatible = "pwm-regulator";
17 regulator-name = "VDDCPU_A";
18 regulator-min-microvolt = <690000>;
19 regulator-max-microvolt = <1050000>;
21 pwm-supply = <&dc_in>;
24 pwm-dutycycle-range = <100 0>;
26 regulator-boot-on;
27 regulator-always-on;
[all …]
H A Dmeson-g12b-odroid.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/input/input.h>
8 #include <dt-bindings/gpio/meson-g12a-gpio.h>
9 #include <dt-bindings/sound/meson-g12a-toacodec.h>
10 #include <dt-bindings/sound/meson-g12a-tohdmitx.h>
20 stdout-path = "serial0:115200n8";
28 emmc_pwrseq: emmc-pwrseq {
29 compatible = "mmc-pwrseq-emmc";
30 reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
33 fan: gpio-fan {
[all …]
H A Dmeson-g12b-a311d-libretech-cc.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
9 #include <dt-bindings/clock/g12a-clkc.h>
10 #include "meson-g12b-a311d.dtsi"
11 #include "meson-libretech-cottonwood.dtsi"
14 compatible = "libretech,aml-a311d-cc", "amlogic,a311d", "amlogic,g12b";
15 model = "Libre Computer AML-A311D-CC Alta";
17 vddcpu_a: regulator-vddcpu-a {
18 compatible = "pwm-regulator";
19 regulator-name = "VDDCPU_A";
[all …]
H A Dmeson-g12b-w400.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include "meson-g12b.dtsi"
11 #include "meson-g12b-s922x.dtsi"
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/gpio/meson-g12a-gpio.h>
22 stdout-path = "serial0:115200n8";
30 emmc_pwrseq: emmc-pwrseq {
31 compatible = "mmc-pwrseq-emmc";
32 reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
[all …]
H A Dmeson-g12b-bananapi-cm4.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include "meson-g12b-a311d.dtsi"
7 #include <dt-bindings/gpio/meson-g12a-gpio.h>
16 stdout-path = "serial0:115200n8";
19 emmc_pwrseq: emmc-pwrseq {
20 compatible = "mmc-pwrseq-emmc";
21 reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
29 sdio_pwrseq: sdio-pwrseq {
30 compatible = "mmc-pwrseq-simple";
31 reset-gpios = <&gpio GPIOAO_6 GPIO_ACTIVE_LOW>;
[all …]
/linux/arch/arm/boot/dts/allwinner/
H A Dsunxi-libretech-all-h3-it.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 // Copyright (C) 2019 Chen-Yu Tsai <wens@csie.org>
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/input/input.h>
14 stdout-path = "serial0:115200n8";
18 compatible = "hdmi-connector";
23 remote-endpoint = <&hdmi_out_con>;
29 compatible = "gpio-leds";
38 compatible = "regulator-fixed";
39 regulator-name = "vcc3v3";
[all …]
H A Dsunxi-libretech-all-h3-cc.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (C) 2017 Chen-Yu Tsai <wens@csie.org>
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/input.h>
16 stdout-path = "serial0:115200n8";
20 compatible = "hdmi-connector";
25 remote-endpoint = <&hdmi_out_con>;
31 compatible = "gpio-leds";
36 default-state = "on";
45 gpio-keys {
[all …]
H A Dsunxi-bananapi-m2-plus-v1.2.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (C) 2018 Chen-Yu Tsai <wens@csie.org>
6 #include "sunxi-bananapi-m2-plus.dtsi"
11 * resistance on the CPU regulator's feedback pin.
13 reg_vdd_cpux: vdd-cpux {
14 compatible = "regulator-gpio";
15 regulator-name = "vdd-cpux";
16 regulator-type = "voltage";
17 regulator-boot-on;
18 regulator-always-on;
[all …]
/linux/arch/arm64/boot/dts/allwinner/
H A Dsun50i-h64-remix-mini-pc.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 /dts-v1/;
6 #include "sun50i-a64.dtsi"
7 #include "sun50i-a64-cpu-opp.dtsi"
9 #include <dt-bindings/gpio/gpio.h>
13 compatible = "jide,remix-mini-pc", "allwinner,sun50i-h64",
14 "allwinner,sun50i-a64";
22 stdout-path = "serial0:115200n8";
25 hdmi-connector {
26 compatible = "hdmi-connector";
[all …]
H A Dsun50i-a64-olinuxino.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 /dts-v1/;
6 #include "sun50i-a64.dtsi"
7 #include "sun50i-a64-cpu-opp.dtsi"
9 #include <dt-bindings/gpio/gpio.h>
12 model = "Olimex A64-Olinuxino";
13 compatible = "olimex,a64-olinuxino", "allwinner,sun50i-a64";
21 stdout-path = "serial0:115200n8";
24 hdmi-connector {
25 compatible = "hdmi-connector";
[all …]
H A Dsun50i-h618-orangepi-zero3.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include "sun50i-h616-orangepi-zero.dtsi"
9 #include "sun50i-h616-cpu-opp.dtsi"
13 compatible = "xunlong,orangepi-zero3", "allwinner,sun50i-h618";
17 cpu-supply = <&reg_dcdc2>;
21 allwinner,tx-delay-ps = <700>;
22 phy-mode = "rgmii-rxid";
23 phy-supply = <&reg_dldo1>;
27 motorcomm,clk-out-frequency-hz = <125000000>;
[all …]
H A Dsun50i-h616-orangepi-zero2.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include "sun50i-h616-orangepi-zero.dtsi"
9 #include "sun50i-h616-cpu-opp.dtsi"
13 compatible = "xunlong,orangepi-zero2", "allwinner,sun50i-h616";
17 cpu-supply = <&reg_dcdca>;
21 allwinner,rx-delay-ps = <3100>;
22 allwinner,tx-delay-ps = <700>;
23 phy-mode = "rgmii";
24 phy-supply = <&reg_dcdce>;
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mn-ddr3l-evk.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
6 #include "imx8mn-evk.dtsi"
7 #include <dt-bindings/interrupt-controller/irq.h>
11 compatible = "fsl,imx8mn-ddr3l-evk", "fsl,imx8mn";
15 cpu-supply = <&buck1>;
19 cpu-supply = <&buck1>;
23 cpu-supply = <&buck1>;
27 cpu-supply = <&buck1>;
34 pinctrl-names = "default";
[all …]
H A Dimx8mn-evk.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
9 #include "imx8mn-evk.dtsi"
10 #include <dt-bindings/interrupt-controller/irq.h>
14 compatible = "fsl,imx8mn-evk", "fsl,imx8mn";
18 cpu-supply = <&buck2>;
22 cpu-supply = <&buck2>;
26 cpu-supply = <&buck2>;
30 cpu-supply = <&buck2>;
37 pinctrl-names = "default";
[all …]
H A Dimx8mn-ddr4-evk.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
9 #include "imx8mn-evk.dtsi"
13 compatible = "fsl,imx8mn-ddr4-evk", "fsl,imx8mn";
17 cpu-supply = <&buck2_reg>;
21 cpu-supply = <&buck2_reg>;
25 cpu-supply = <&buck2_reg>;
29 cpu-supply = <&buck2_reg>;
33 operating-points-v2 = <&ddrc_opp_table>;
35 ddrc_opp_table: opp-table {
[all …]
/linux/arch/arm64/boot/dts/rockchip/
H A Drk3588-friendlyelec-cm3588.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/leds/common.h>
13 #include <dt-bindings/pinctrl/rockchip.h>
26 stdout-path = "serial2:1500000n8";
30 compatible = "gpio-leds";
32 led_sys: led-0 {
36 linux,default-trigger = "heartbeat";
37 pinctrl-names = "default";
[all …]
H A Drk3399-kobol-helios64.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
13 /dts-v1/;
26 avdd_0v9_s0: regulator-avdd-0v9-s0 {
27 compatible = "regulator-fixed";
28 regulator-name = "avdd_0v9_s0";
29 regulator-always-on;
30 regulator-boot-on;
31 regulator-min-microvolt = <900000>;
32 regulator-max-microvolt = <900000>;
33 vin-supply = <&vcc1v8_sys_s3>;
[all …]
H A Drk3566-box-demo.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/leds/common.h>
12 #include <dt-bindings/pinctrl/rockchip.h>
13 #include <dt-bindings/soc/rockchip,vop2.h>
18 compatible = "rockchip,rk3566-box-demo", "rockchip,rk3566";
28 stdout-path = "serial2:1500000n8";
31 gmac1_clkin: external-gmac1-clock {
32 compatible = "fixed-clock";
[all …]
H A Dpx30-firefly-jd4-core.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/pinctrl/rockchip.h>
11 compatible = "firefly,px30-jd4-core", "rockchip,px30";
13 emmc_pwrseq: emmc-pwrseq {
14 compatible = "mmc-pwrseq-emmc";
15 pinctrl-0 = <&emmc_reset>;
16 pinctrl-names = "default";
17 reset-gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>;
20 vcc5v0_sys: regulator-vcc5v0-sys {
[all …]
/linux/arch/arm/boot/dts/rockchip/
H A Drv1126-sonoff-ihost.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include "rv1126-sonoff-ihost.dtsi"
12 compatible = "itead,sonoff-ihost", "rockchip,rv1126";
16 cpu-supply = <&vdd_arm>;
20 cpu-supply = <&vdd_arm>;
24 cpu-supply = <&vdd_arm>;
28 cpu-supply = <&vdd_arm>;

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