| /linux/Documentation/scheduler/ |
| H A D | sched-capacity.rst | 2 Capacity Aware Scheduling
5 1. CPU Capacity
9 ----------------
13 different performance characteristics - on such platforms, not all CPUs can be
16 CPU capacity is a measure of the performance a CPU can reach, normalized against
17 the most performant CPU in the system. Heterogeneous systems are also called
18 asymmetric CPU capacity systems, as they contain CPUs of different capacities.
20 Disparity in maximum attainable performance (IOW in maximum CPU capacity) stems
23 - not all CPUs may have the same microarchitecture (µarch).
24 - with Dynamic Voltage and Frequency Scaling (DVFS), not all CPUs may be
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| H A D | sched-energy.rst | 6 ---------------
10 Energy Model (EM) of the CPUs to select an energy efficient CPU for each task,
17 /!\ EAS does not support platforms with symmetric CPU topologies /!\
19 EAS operates only on heterogeneous CPU topologies (such as Arm big.LITTLE)
25 please refer to its documentation (see Documentation/power/energy-model.rst).
29 -----------------------------
32 - energy = [joule] (resource like a battery on powered devices)
33 - power = energy/time = [joule/second] = [watt]
39 --------------------
45 -----------
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| H A D | schedutil.rst | 7 All this assumes a linear relation between frequency and work capacity,
15 individual tasks to task-group slices to CPU runqueues. As the basis for this
31 Note that blocked tasks still contribute to the aggregates (task-group slices
32 and CPU runqueues), which reflects their expected contribution when they
36 reflects the time an entity spends on the CPU, while 'runnable' reflects the
38 two metrics are the same, but once there is contention for the CPU 'running'
39 will decrease to reflect the fraction of time each task spends on the CPU
45 Frequency / CPU Invariance
48 Because consuming the CPU for 50% at 1GHz is not the same as consuming the CPU
49 for 50% at 2GHz, nor is running 50% on a LITTLE CPU the same as running 50% on
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| /linux/Documentation/devicetree/bindings/cpu/ |
| H A D | cpu-capacity.txt | 2 CPU capacity bindings
6 1 - Introduction
15 2 - CPU capacity definition
18 CPU capacity is a number that provides the scheduler information about CPUs
19 heterogeneity. Such heterogeneity can come from micro-architectural differences
23 capture a first-order approximation of the relative performance of CPUs.
25 CPU capacities are obtained by running a suitable benchmark. This binding makes
27 final capacity should, however, be:
29 * A "single-threaded" or CPU affine benchmark
30 * Divided by the running frequency of the CPU executing the benchmark
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| /linux/arch/arm/kernel/ |
| H A D | topology.c | 15 #include <linux/cpu.h>
29 #include <asm/cpu.h>
34 * cpu capacity scale management
38 * cpu capacity table
39 * This per cpu data structure describes the relative capacity of each core.
40 * On a heteregenous system, cores don't have the same computation capacity
42 * can take this difference into account during load balance. A per cpu
43 * structure is preferred because each CPU updates its own cpu_capacity field
61 * is used to compute the capacity of a CPU.
66 {"arm,cortex-a15", 3891},
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| /linux/Documentation/translations/zh_CN/scheduler/ |
| H A D | sched-capacity.rst | 1 .. SPDX-License-Identifier: GPL-2.0
2 .. include:: ../disclaimer-zh_CN.rst
4 :Original: Documentation/scheduler/sched-capacity.rst
22 --------
27 我们引入CPU算力（capacity）的概念来测量每个CPU能达到的性能，它的值相对系统中性能最强的CPU
32 - 不是所有CPU的微架构都相同。
33 - 在动态电压频率升降（Dynamic Voltage and Frequency Scaling，DVFS）框架中，不是所有的CPU都
34 能达到一样高的操作性能值（Operating Performance Points，OPP。译注，也就是“频率-电压”对）。
42 capacity(cpu) = work_per_hz(cpu) * max_freq(cpu)
45 --------------
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| /linux/drivers/base/ |
| H A D | arch_topology.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Arch specific cpu topology information
12 #include <linux/cpu.h>
66 int cpu; in topology_set_scale_freq_source() local
77 for_each_cpu(cpu, cpus) { in topology_set_scale_freq_source()
78 sfd = rcu_dereference(*per_cpu_ptr(&sft_data, cpu)); in topology_set_scale_freq_source()
81 if (!sfd || sfd->source != SCALE_FREQ_SOURCE_ARCH) { in topology_set_scale_freq_source()
82 rcu_assign_pointer(per_cpu(sft_data, cpu), data); in topology_set_scale_freq_source()
83 cpumask_set_cpu(cpu, &scale_freq_counters_mask); in topology_set_scale_freq_source()
97 int cpu; in topology_clear_scale_freq_source() local
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| /linux/arch/arm/boot/dts/samsung/ |
| H A D | exynos5422-cpus.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung Exynos5422 SoC cpu device tree source
8 * This file provides desired ordering for Exynos5422: CPU[0123] being the A7.
10 * The Exynos5420, 5422 and 5800 actually share the same CPU configuration
13 * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422
15 * the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting
16 * from the LITTLE: Cortex-A7.
21 #address-cells = <1>;
22 #size-cells = <0>;
24 cpu-map {
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| H A D | exynos5420-cpus.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung Exynos5420 SoC cpu device tree source
9 * boards: CPU[0123] being the A15.
11 * The Exynos5420, 5422 and 5800 actually share the same CPU configuration
14 * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422
16 * the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting
17 * from the LITTLE: Cortex-A7.
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
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| /linux/arch/arm64/boot/dts/amlogic/ |
| H A D | meson-gxm.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include "meson-gxl.dtsi"
10 compatible = "amlogic,meson-gxm";
13 cpu-map {
16 cpu = <&cpu0>;
19 cpu = <&cpu1>;
22 cpu = <&cpu2>;
25 cpu = <&cpu3>;
31 cpu = <&cpu4>;
34 cpu = <&cpu5>;
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| H A D | meson-g12b.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include "meson-g12.dtsi"
13 #address-cells = <0x2>;
14 #size-cells = <0x0>;
16 cpu-map {
19 cpu = <&cpu0>;
23 cpu = <&cpu1>;
29 cpu = <&cpu100>;
33 cpu = <&cpu101>;
37 cpu = <&cpu102>;
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| /linux/arch/arm64/boot/dts/apple/ |
| H A D | t6002.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/apple-aic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/pinctrl/apple.h>
15 #include "multi-die-cpp.h"
17 #include "t600x-common.dtsi"
20 compatible = "apple,t6002", "apple,arm-platform";
22 #address-cells = <2>;
23 #size-cells = <2>;
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| H A D | t600x-common.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
11 #address-cells = <2>;
12 #size-cells = <2>;
15 #address-cells = <2>;
16 #size-cells = <0>;
18 cpu-map {
21 cpu = <&cpu_e00>;
24 cpu = <&cpu_e01>;
30 cpu = <&cpu_p00>;
33 cpu = <&cpu_p01>;
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| /linux/arch/s390/kernel/ |
| H A D | hiperdispatch.c | 1 // SPDX-License-Identifier: GPL-2.0
11 * Dynamically calculates the optimum number of high capacity COREs
13 * that a capacity update is necessary, it schedules a topology update.
14 * During topology updates the CPU capacities are always re-adjusted.
16 * There is two places where CPU capacities are being accessed within
18 * -> hiperdispatch's reoccuring work function reads CPU capacities to
19 * determine high capacity CPU count.
20 * -> during a topology update hiperdispatch's adjustment function
21 * updates CPU capacities.
33 * of them high capacity.
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| /linux/arch/x86/kernel/cpu/ |
| H A D | aperfmperf.c | 1 // SPDX-License-Identifier: GPL-2.0-only
20 #include <asm/cpu.h>
22 #include <asm/intel-family.h>
24 #include "cpu.h"
58 * Since the frequency freq_curr on x86 is controlled by micro-controller and
59 * our P-state setting is little more than a request/hint, we need to observe
65 * where freq_base is the max non-turbo P-state.
178 fratio -= delta_fratio; in knl_set_max_freq_ratio()
234 /* The CPU may have less than 4 cores */ in core_set_max_freq_ratio()
274 …pr_debug("Couldn't determine cpu base or turbo frequency, necessary for scale-invariant accounting… in intel_set_max_freq_ratio()
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| /linux/include/linux/sched/ |
| H A D | sd_flags.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * sched-domains (multiprocessor balancing) flag declarations.
29 * certain level (e.g. domain starts spanning CPUs outside of the base CPU's
78 * Consider waking task on waking CPU.
85 * Domain members have different CPU capacities
89 * NEEDS_GROUPS: Per-CPU capacity is asymmetric between groups.
94 * Domain members have different CPU capacities spanning all unique CPU
95 * capacity values.
98 * all available CPU capacities are visible
99 * NEEDS_GROUPS: Per-CPU capacity is asymmetric between groups.
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| /linux/arch/arm64/boot/dts/arm/ |
| H A D | juno-r2.dts | 9 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/arm/coresight-cti-dt.h>
13 #include "juno-base.dtsi"
14 #include "juno-cs-r1r2.dtsi"
18 compatible = "arm,juno-r2", "arm,juno", "arm,vexpress";
19 interrupt-parent = <&gic>;
20 #address-cells = <2>;
21 #size-cells = <2>;
28 stdout-path = "serial0:115200n8";
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| H A D | juno.dts | 4 * Copyright (c) 2013-2014 ARM Ltd.
9 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/arm/coresight-cti-dt.h>
13 #include "juno-base.dtsi"
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
27 stdout-path = "serial0:115200n8";
31 compatible = "arm,psci-0.2";
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| H A D | juno-r1.dts | 9 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/arm/coresight-cti-dt.h>
13 #include "juno-base.dtsi"
14 #include "juno-cs-r1r2.dtsi"
18 compatible = "arm,juno-r1", "arm,juno", "arm,vexpress";
19 interrupt-parent = <&gic>;
20 #address-cells = <2>;
21 #size-cells = <2>;
28 stdout-path = "serial0:115200n8";
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| /linux/lib/ |
| H A D | objpool.c | 1 // SPDX-License-Identifier: GPL-2.0
12 * objpool: ring-array based lockless MPMC/FIFO queues
24 void *obj = (void *)&slot->entries[pool->capacity]; in objpool_init_percpu_slot()
28 slot->mask = pool->capacity - 1; in objpool_init_percpu_slot()
36 slot->entries[slot->tail & slot->mask] = obj; in objpool_init_percpu_slot()
37 obj = obj + pool->obj_size; in objpool_init_percpu_slot()
38 slot->tail++; in objpool_init_percpu_slot()
39 slot->last = slot->tail; in objpool_init_percpu_slot()
40 pool->nr_objs++; in objpool_init_percpu_slot()
58 /* skip the cpu node which could never be present */ in objpool_init_percpu_slots()
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| /linux/Documentation/devicetree/bindings/riscv/ |
| H A D | cpus.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V CPUs
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 This document uses some terminology common to the RISC-V community
19 mandated by the RISC-V ISA: a PC and some registers. This
27 - $ref: /schemas/cpu.yaml#
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| /linux/kernel/sched/ |
| H A D | fair.c | 1 // SPDX-License-Identifier: GPL-2.0
43 #include <linux/memory-tiers.h>
59 * The initial- and re-scaling of tunables is configurable
63 * SCHED_TUNABLESCALING_NONE - unscaled, always *1
64 * SCHED_TUNABLESCALING_LOG - scaled logarithmically, *1+ilog(ncpus)
65 * SCHED_TUNABLESCALING_LINEAR - scaled linear, *ncpus
72 * Minimal preemption granularity for CPU-bound tasks:
90 * For asym packing, by default the lower numbered CPU has higher priority.
92 int __weak arch_asym_cpu_priority(int cpu) in arch_asym_cpu_priority() argument
94 return -cpu; in arch_asym_cpu_priority()
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| H A D | topology.c | 1 // SPDX-License-Identifier: GPL-2.0
35 static int sched_domain_debug_one(struct sched_domain *sd, int cpu, int level, in sched_domain_debug_one() argument
38 struct sched_group *group = sd->groups; in sched_domain_debug_one()
39 unsigned long flags = sd->flags; in sched_domain_debug_one()
44 printk(KERN_DEBUG "%*s domain-%d: ", level, "", level); in sched_domain_debug_one()
46 cpumask_pr_args(sched_domain_span(sd)), sd->name); in sched_domain_debug_one()
48 if (!cpumask_test_cpu(cpu, sched_domain_span(sd))) { in sched_domain_debug_one()
49 printk(KERN_ERR "ERROR: domain->span does not contain CPU%d\n", cpu); in sched_domain_debug_one()
51 if (group && !cpumask_test_cpu(cpu, sched_group_span(group))) { in sched_domain_debug_one()
52 printk(KERN_ERR "ERROR: domain->groups does not contain CPU%d\n", cpu); in sched_domain_debug_one()
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| /linux/Documentation/devicetree/bindings/opp/ |
| H A D | opp-v2-kryo-cpu.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/opp/opp-v2-kryo-cpu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ilia Lin <ilia.lin@kernel.org>
13 - $ref: opp-v2-base.yaml#
17 the CPU frequencies subset and voltage value of each OPP varies based on
22 The qcom-cpufreq-nvmem driver reads the efuse value from the SoC to provide
25 operating-points-v2 table when it is parsed by the OPP framework.
30 - operating-points-v2-krait-cpu
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| /linux/Documentation/admin-guide/pm/ |
| H A D | cpufreq.rst | 1 .. SPDX-License-Identifier: GPL-2.0
7 CPU Performance Scaling
15 The Concept of CPU Performance Scaling
20 Operating Performance Points or P-states (in ACPI terminology). As a rule,
22 can be retired by the CPU over a unit of time, but also the higher the clock
24 time (or the more power is drawn) by the CPU in the given P-state. Therefore
25 there is a natural tradeoff between the CPU capacity (the number of instructions
26 that can be executed over a unit of time) and the power drawn by the CPU.
29 as possible and then there is no reason to use any P-states different from the
30 highest one (i.e. the highest-performance frequency/voltage configuration
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