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/linux/tools/testing/selftests/cpu-hotplug/
H A Dcpu-on-off-test.sh2 # SPDX-License-Identifier: GPL-2.0
5 # Kselftest framework requirement - SKIP code is 4.
14 echo $msg must be run as root >&2
18 taskset -p 01 $$
20 SYSFS=`mount -t sysfs | head -1 | awk '{ print $3 }'`
22 if [ ! -d "$SYSFS" ]; then
23 echo $msg sysfs is not mounted >&2
27 if ! ls $SYSFS/devices/system/cpu/cpu* > /dev/null 2>&1; then
28 echo $msg cpu hotplug is not supported >&2
32 echo "CPU online/offline summary:"
[all …]
/linux/tools/perf/pmu-events/arch/s390/cf_z17/
H A Dextended.json3 "Unit": "CPU-M-CF",
6 "BriefDescription": "L1D Read-only Exclusive Writes",
7 …blicDescription": "A directory write to the Level-1 Data cache where the line was originally in a …
10 "Unit": "CPU-M-CF",
14 …s been written into The Translation Lookaside Buffer 2 (TLB2) and the request was made by the Leve…
17 "Unit": "CPU-M-CF",
21 …ress for a request made by the Level-1 Data cache. Incremented by one for every TLB2 miss in progr…
24 "Unit": "CPU-M-CF",
28 … into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte page…
31 "Unit": "CPU-M-CF",
[all …]
/linux/tools/perf/pmu-events/arch/s390/cf_z16/
H A Dextended.json3 "Unit": "CPU-M-CF",
6 "BriefDescription": "L1D Read-only Exclusive Writes",
7 …blicDescription": "A directory write to the Level-1 Data cache where the line was originally in a …
10 "Unit": "CPU-M-CF",
14 …s been written into The Translation Lookaside Buffer 2 (TLB2) and the request was made by the Leve…
17 "Unit": "CPU-M-CF",
21 …ress for a request made by the Level-1 Data cache. Incremented by one for every TLB2 miss in progr…
24 "Unit": "CPU-M-CF",
28 … into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte page…
31 "Unit": "CPU-M-CF",
[all …]
/linux/Documentation/translations/zh_CN/mm/
H A Dmmu_notifier.rst28 - 上页表锁
29 - 清除页表项并通知 ([pmd/pte]p_huge_clear_flush_notify())
30 - 设置页表项以指向新页
37 两个地址addrA和addrB，这样|addrA - addrB| >= PAGE_SIZE，我们假设它们是COW的
42 [Time N] --------------------------------------------------------------------
43 CPU-thread-0 {尝试写到addrA}
44 CPU-thread-1 {尝试写到addrB}
45 CPU-thread-2 {}
46 CPU-thread-3 {}
47 DEV-thread-0 {读取addrA并填充设备TLB}
[all …]
/linux/arch/arm64/boot/dts/hisilicon/
H A Dhip05.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip05-d02";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
[all …]
H A Dhip07.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip07-d05";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
[all …]
/linux/Documentation/mm/
H A Dmmu_notifier.rst8 For secondary TLB (non CPU TLB) like IOMMU TLB or device TLB (when device use
9 thing like ATS/PASID to get the IOMMU to walk the CPU page table to access a
10 process virtual address space). There is only 2 cases when you need to notify
23 - take page table lock
24 - clear page table entry and notify ([pmd/pte]p_huge_clear_flush_notify())
25 - set page table entry to point to new page
33 Two address addrA and addrB such that \|addrA - addrB\| >= PAGE_SIZE we assume
38 [Time N] --------------------------------------------------------------------
39 CPU-thread-0 {try to write to addrA}
40 CPU-thread-1 {try to write to addrB}
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls2088a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-2088A family SoC.
12 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
13 #include "fsl-ls208xa.dtsi"
17 compatible = "arm,cortex-a72-pmu";
22 &cpu {
23 cpu0: cpu@0 {
24 device_type = "cpu";
25 compatible = "arm,cortex-a72";
28 cpu-idle-states = <&CPU_PW20>;
[all …]
H A Dfsl-ls2080a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-2080A family SoC.
5 * Copyright 2014-2016 Freescale Semiconductor, Inc.
12 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
13 #include "fsl-ls208xa.dtsi"
17 compatible = "arm,cortex-a57-pmu";
22 &cpu {
23 cpu0: cpu@0 {
24 device_type = "cpu";
25 compatible = "arm,cortex-a57";
[all …]
/linux/arch/arm64/boot/dts/amd/
H A Delba-16core.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 * Copyright 2020-2023 Advanced Micro Devices, Inc.
8 #address-cells = <1>;
9 #size-cells = <0>;
11 cpu-map {
13 core0 { cpu = <&cpu0>; };
14 core1 { cpu = <&cpu1>; };
15 core2 { cpu = <&cpu2>; };
16 core3 { cpu = <&cpu3>; };
20 core0 { cpu = <&cpu4>; };
[all …]
/linux/tools/testing/selftests/net/forwarding/
H A Dtsn_lib.sh2 # SPDX-License-Identifier: GPL-2.0
3 # Copyright 2021-2022 NXP
5 tc_testing_scripts_dir=$(dirname $0)/../../tc-testing/scripts
15 # https://github.com/vladimiroltean/tsn-scripts
16 # WARNING: isochron versions pre-1.0 are unstable,
31 if ! [ -z "${uds_address}" ]; then
32 extra_args="${extra_args} -z ${uds_address}"
37 chrt -f 10 phc2sys -m \
38 -a -rr \
39 --step_threshold 0.00002 \
[all …]
/linux/arch/arm64/boot/dts/cavium/
H A Dthunder-88xx.dtsi2 * Cavium Thunder DTS file - Thunder SoC description
6 * This file is dual-licensed: you can use it either under the terms
13 * published by the Free Software Foundation; either version 2 of the
24 * MA 02110-1301 USA
51 compatible = "cavium,thunder-88xx";
52 interrupt-parent = <&gic0>;
53 #address-cells = <2>;
54 #size-cells = <2>;
57 compatible = "arm,psci-0.2";
62 #address-cells = <2>;
[all …]
/linux/arch/arm/boot/dts/samsung/
H A Dexynos5422-cpus.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung Exynos5422 SoC cpu device tree source
8 * This file provides desired ordering for Exynos5422: CPU[0123] being the A7.
10 * The Exynos5420, 5422 and 5800 actually share the same CPU configuration
13 * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422
15 * the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting
16 * from the LITTLE: Cortex-A7.
21 #address-cells = <1>;
22 #size-cells = <0>;
24 cpu-map {
[all …]
H A Dexynos5420-cpus.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung Exynos5420 SoC cpu device tree source
9 * boards: CPU[0123] being the A15.
11 * The Exynos5420, 5422 and 5800 actually share the same CPU configuration
14 * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422
16 * the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting
17 * from the LITTLE: Cortex-A7.
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
[all …]
/linux/tools/testing/selftests/drivers/net/
H A Dnetcons_sysdata.sh2 # SPDX-License-Identifier: GPL-2.0
4 # A test that makes sure that sysdata runtime CPU data is properly set
7 # There are 3 different tests, every time sent using a random CPU.
8 # - Test #1
10 # - Test #2
12 # - Test #3
17 set -euo pipefail
19 SCRIPTDIR=$(dirname "$(readlink -e "${BASH_SOURCE[0]}")")
25 if [[ ! -f "${NETCONS_PATH}/userdata/cpu_nr_enabled" ]]
27 echo "Populate CPU configfs path not available in ${NETCONS_PATH}/userdata/cpu_nr_enabled" >&2
[all …]
/linux/Documentation/devicetree/bindings/cpu/
H A Dcpu-capacity.txt2 CPU capacity bindings
6 1 - Introduction
15 2 - CPU capacity definition
18 CPU capacity is a number that provides the scheduler information about CPUs
19 heterogeneity. Such heterogeneity can come from micro-architectural differences
23 capture a first-order approximation of the relative performance of CPUs.
25 CPU capacities are obtained by running a suitable benchmark. This binding makes
29 * A "single-threaded" or CPU affine benchmark
30 * Divided by the running frequency of the CPU executing the benchmark
31 * Not subject to dynamic frequency scaling of the CPU
[all …]
/linux/Documentation/translations/ko_KR/
H A Dmemory-barriers.txt2 This is a version of Documentation/memory-barriers.txt translated into Korean.
15 Documentation/memory-barriers.txt
39 일부 이상한 점들은 공식적인 메모리 일관성 모델과 tools/memory-model/ 에 있는
51 (2) 사용 가능한 배리어들에 대해 어떻게 사용해야 하는지에 대한 안내를 제공하기
60 해당 배리어의 명시적 사용이 불필요해서 no-op 이 될수도 있음을 알아두시기
76 - 디바이스 오퍼레이션.
77 - 보장사항.
81 - 메모리 배리어의 종류.
82 - 메모리 배리어에 대해 가정해선 안될 것.
83 - 주소 데이터 의존성 배리어 (역사적).
[all …]
/linux/Documentation/translations/zh_TW/arch/arm64/
H A Dbooting.txt1 SPDX-License-Identifier: GPL-2.0
15 ---------------------------------------------------------------------
30 ---------------------------------------------------------------------
40 AArch64 異常模型由多個異常級（EL0 - EL3）組成，對於 EL0 和 EL1 異常級
45 這個術語來定義在將控制權交給 Linux 內核前 CPU 上執行的所有軟件。
52 2、設置設備樹數據
58 -----------------
68 2、設置設備樹數據
69 ---------------
73 設備樹數據塊（dtb）必須 8 字節對齊，且大小不能超過 2MB。由於設備樹
[all …]
/linux/Documentation/translations/zh_CN/arch/arm64/
H A Dbooting.txt12 ---------------------------------------------------------------------
26 ---------------------------------------------------------------------
36 AArch64 异常模型由多个异常级（EL0 - EL3）组成，对于 EL0 和 EL1 异常级
41 这个术语来定义在将控制权交给 Linux 内核前 CPU 上执行的所有软件。
48 2、设置设备树数据
54 -----------------
64 2、设置设备树数据
65 ---------------
69 设备树数据块（dtb）必须 8 字节对齐，且大小不能超过 2MB。由于设备树
70 数据块将在使能缓存的情况下以 2MB 粒度被映射，故其不能被置于必须以特定
[all …]
/linux/Documentation/devicetree/bindings/opp/
H A Dopp-v2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/opp/opp-v2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Viresh Kumar <viresh.kumar@linaro.org>
13 - $ref: opp-v2-base.yaml#
17 const: operating-points-v2
22 - |
24 * Example 1: Single cluster Dual-core ARM cortex A9, switch DVFS states
28 #address-cells = <1>;
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/linux/tools/perf/pmu-events/arch/x86/grandridge/
H A Duncore-io.json4 "Counter": "0,1,2,3",
13 "Counter": "0,1,2,3",
25 "Counter": "0,1,2,3",
37 "Counter": "0,1,2,3",
49 "Counter": "0,1,2,3",
61 "Counter": "0,1,2,3",
73 "Counter": "0,1,2,3",
85 "Counter": "0,1,2,3",
97 "Counter": "0,1,2,3",
109 "Counter": "0,1,2,3",
[all …]
/linux/arch/mips/loongson64/
H A Dsmp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/cpu.h>
37 static u32 (*ipi_read_clear)(int cpu);
38 static void (*ipi_write_action)(int cpu, u32 action);
39 static void (*ipi_write_enable)(int cpu);
40 static void (*ipi_clear_buf)(int cpu);
41 static void (*ipi_write_buf)(int cpu, struct task_struct *idle);
43 /* send mail via Mail_Send register for 3A4000+ CPU */
44 static void csr_mail_send(uint64_t data, int cpu, int mailbox) in csr_mail_send() argument
51 val |= (cpu << CSR_MAIL_SEND_CPU_SHIFT); in csr_mail_send()
[all …]
/linux/arch/arm64/boot/dts/apple/
H A Dt6002.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
5 * Other names: H13J, "Jade 2C"
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/apple-aic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/pinctrl/apple.h>
14 #include <dt-bindings/spmi/spmi.h>
16 #include "multi-die-cpp.h"
18 #include "t600x-common.dtsi"
21 compatible = "apple,t6002", "apple,arm-platform";
[all …]
/linux/tools/perf/pmu-events/arch/x86/graniterapids/
H A Duncore-io.json4 "Counter": "0,1,2,3",
13 "Counter": "0,1,2,3",
25 "Counter": "0,1,2,3",
37 "Counter": "0,1,2,3",
49 "Counter": "0,1,2,3",
61 "Counter": "0,1,2,3",
73 "Counter": "0,1,2,3",
85 "Counter": "0,1,2,3",
97 "Counter": "0,1,2,3",
109 "Counter": "0,1,2,3",
[all …]
/linux/tools/perf/pmu-events/arch/x86/sierraforest/
H A Duncore-io.json4 "Counter": "0,1,2,3",
13 "Counter": "0,1,2,3",
25 "Counter": "0,1,2,3",
37 "Counter": "0,1,2,3",
49 "Counter": "0,1,2,3",
61 "Counter": "0,1,2,3",
73 "Counter": "0,1,2,3",
85 "Counter": "0,1,2,3",
97 "Counter": "0,1,2,3",
109 "Counter": "0,1,2,3",
[all …]

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