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/linux/tools/lib/perf/Documentation/
H A D	libperf-counting.txt	1 libperf-counting(7) 6 libperf-counting - counting interface 10 The counting interface provides API to measure and get count for specific perf events. 12 The following test tries to explain count on `counting.c` example. 14 It is by no means complete guide to counting, but shows libperf basic API for counting. 16 The `counting.c` comes with libperf package and can be compiled and run like: 20 $ gcc -o counting counting.c -lperf 21 $ sudo ./counting 29 The `counting.c` example monitors two events on the current process and displays 158 From this moment events are counting and we can do our workload.
/linux/tools/perf/pmu-events/arch/x86/broadwellx/
H A D	frontend.json	42 "PublicDescription": "This event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes UC accesses.", 52 "PublicDescription": "This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.", 62 "PublicDescription": "This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.", 72 "PublicDescription": "This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", 82 "PublicDescription": "This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", 92 "PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.", 101 "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.", 119 "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", 129 "PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ.", 138 "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting include [all...]
/linux/tools/perf/pmu-events/arch/x86/broadwellde/
H A D	frontend.json	42 "PublicDescription": "This event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes UC accesses.", 52 "PublicDescription": "This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.", 62 "PublicDescription": "This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.", 72 "PublicDescription": "This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", 82 "PublicDescription": "This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", 92 "PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.", 101 "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.", 119 "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", 129 "PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ.", 138 "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting include [all...]
/linux/tools/perf/pmu-events/arch/x86/broadwell/
H A D	frontend.json	42 "PublicDescription": "This event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes UC accesses.", 52 "PublicDescription": "This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.", 62 "PublicDescription": "This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.", 72 "PublicDescription": "This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", 82 "PublicDescription": "This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", 92 "PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.", 101 "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.", 119 "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", 129 "PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ.", 138 "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting include [all...]
/linux/Documentation/ABI/testing/
H A D	sysfs-bus-iio-timer-stm32	`99 When counting up the counter starts from 0 and fires an 101 When counting down the counter start from preset value 115 counting direction is set by in_count0_count_direction 122 Counting is enabled when connected trigger signal 123 level is high else counting is disabled. 126 Counting is enabled on rising edge of the connected 141 counting direction is set by in_count0_count_direction`
/linux/Documentation/devicetree/bindings/timer/
H A D	renesas,rz-mtu3.yaml	36 - Phase counting mode can be specified independently 37 - 32-bit phase counting mode can be specified for interlocked operation 57 - 32-bit phase counting mode specifiable by combining MTU1 and MTU2 and 75 There are two phase counting modes. 16-bit phase counting mode in which 77 counting mode in which MTU1 and MTU2 are cascaded. 79 In phase counting mode, the phase difference between two external input 83 count0 - MTU1 16-bit phase counting 84 count1 - MTU2 16-bit phase counting 85 count2 - MTU1+ MTU2 32-bit phase counting
/linux/include/asm-generic/bitops/
H A D	instrumented-non-atomic.h	`19 * @addr: the address to start counting from 35 * @addr: the address to start counting from 51 * @addr: the address to start counting from 136 * @addr: Address to start counting from 148 * @addr: Address to start counting from`
H A D	generic-non-atomic.h	`21 * @addr: the address to start counting from 48 * @addr: the address to start counting from 118 * @addr: Address to start counting from 134 * @addr: Address to start counting from 158 * @addr: Address to start counting from`
H A D	instrumented-atomic.h	`19 * @addr: the address to start counting from 35 * @addr: Address to start counting from 48 * @addr: Address to start counting from`
H A D	lock.h	`36 * @addr: the address to start counting from 50 * @addr: the address to start counting from`
/linux/tools/perf/pmu-events/arch/x86/silvermont/
H A D	virtual-memory.json	`36 …age walk implies a TLB miss, the number of TLB misses can be counted by counting the number of pag… 55 …age walk implies a TLB miss, the number of TLB misses can be counted by counting the number of pag… 65 …age walk implies a TLB miss, the number of TLB misses can be counted by counting the number of pag…`
/linux/tools/perf/pmu-events/arch/x86/skylake/
H A D	frontend.json	323 …ruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. Counting includes uops tha… 333 …ruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. Counting includes uops tha… 343 …nstruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops tha… 372 …nstruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops tha… 382 …e being delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops tha… 391 …of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops tha… 401 …truction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops tha… 411 …truction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops tha… 420 …truction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops tha… 449 …uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover ca…
/linux/tools/perf/pmu-events/arch/x86/cascadelakex/
H A D	frontend.json	323 …ruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. Counting includes uops tha… 333 …ruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. Counting includes uops tha… 343 …nstruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops tha… 372 …nstruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops tha… 382 …e being delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops tha… 391 …of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops tha… 401 …truction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops tha… 411 …truction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops tha… 420 …truction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops tha… 449 …uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover ca…
/linux/tools/perf/pmu-events/arch/x86/skylakex/
H A D	frontend.json	323 …ruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. Counting includes uops tha… 333 …ruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. Counting includes uops tha… 343 …nstruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops tha… 372 …nstruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops tha… 382 …e being delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops tha… 391 …of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops tha… 401 …truction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops tha… 411 …truction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops tha… 420 …truction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops tha… 449 …uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover ca…
/linux/drivers/comedi/drivers/
H A D	comedi_8254.c	`51 * In addition I8254_BCD and I8254_BINARY specify the counting mode: 52 * I8254_BCD BCD counting 53 * I8254_BINARY Binary counting 59 * for binary counting and 10^4 for BCD counting. 63 * for binary counting or 9999 for BCD counting, and continues counting. 65 * count and continues counting from there.`
/linux/tools/include/asm-generic/bitops/
H A D	non-atomic.h	`10 * @addr: the address to start counting from 37 * @addr: the address to start counting from 107 * @addr: Address to start counting from`
/linux/arch/mips/lib/
H A D	bitops.c	`19 * @addr: the address to start counting from 40 * @addr: Address to start counting from 61 * @addr: Address to start counting from`
/linux/Documentation/admin-guide/perf/
H A D	alibaba_pmu.rst	`53 By counting the READ, WRITE and RMW commands sent to the DDRC through the HIF 54 interface, we could calculate the bandwidth. Example usage of counting memory 91 Example usage of counting all memory read/write bandwidth by metric::`
/linux/arch/riscv/include/asm/
H A D	bitops.h	`264 * @addr: the address to start counting from 281 * @addr: Address to start counting from 295 * @addr: Address to start counting from 323 * @addr: the address to start counting from 336 * @addr: the address to start counting from`
/linux/tools/perf/
H A D	design.txt	`152 Counters come in two flavours: counting counters and sampling 153 counters. A "counting" counter is one that is used for counting the 225 way to request that counting of events be restricted to times when the 229 to request counting of events restricted to guest and host contexts when 433 non-leader stops that counter from counting but doesn't affect any`
/linux/drivers/counter/
H A D	rz-mtu3-cnt.c	31 #define RZ_MTU3_TMDR1_PH_CNT_MODE_1 (4) /* Phase counting mode 1 / 32 #define RZ_MTU3_TMDR1_PH_CNT_MODE_2 (5) / Phase counting mode 2 / 33 #define RZ_MTU3_TMDR1_PH_CNT_MODE_3 (6) / Phase counting mode 3 / 34 #define RZ_MTU3_TMDR1_PH_CNT_MODE_4 (7) / Phase counting mode 4 / 35 #define RZ_MTU3_TMDR1_PH_CNT_MODE_5 (9) / Phase counting mode 5 / 398 / Phase counting mode 1 is used as default in initialization. / in rz_mtu3_32bit_cnt_setting() 412 / Phase counting mode 1 is used as default in initialization. / in rz_mtu3_16bit_cnt_setting() 436 32-bit phase counting need MTU1 and MTU2 to create 32-bit in rz_mtu3_initialize_counter()
/linux/include/linux/sched/
H A D	loadavg.h	`7 * counting. Some notes: 11 * precision, or rounding will get you. With 2-second counting freq,`
/linux/tools/include/nolibc/
H A D	stdlib.h	`193 * (not counting the trailing zero) is returned. The function is constructed 233 * number of characters emitted (not counting the trailing zero) is returned. 264 * number of characters emitted (not counting the trailing zero) is returned. 324 * the first byte, and the number of characters emitted (not counting the 368 * the first byte, and the number of characters emitted (not counting the 399 * the first byte, and the number of characters emitted (not counting the`
/linux/Documentation/arch/arm64/
H A D	perf.rst	`66 must enable/disable counting on the entry and exit to the guest. This is 88 able to eliminate counters counting host events on the boundaries of guest 89 entry/exit when counting guest events by filtering out EL2 for 168 Event Counting Threshold`
/linux/arch/mips/include/asm/
H A D	bitops.h	`82 * @addr: the address to start counting from 110 * @addr: Address to start counting from 138 * @addr: Address to start counting from 152 * @addr: Address to start counting from 313 * @addr: Address to start counting from`

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