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Searched full:counter0 (Results 1 – 12 of 12) sorted by relevance

/linux/arch/powerpc/kernel/vdso/
H A Dvgetrandom-chacha.S32 #define counter0 r14 macro
174 lwz counter0, 0(counter)
177 rldimi counter0, counter1, 32, 0
215 mr state12, counter0
245 add state12, state12, counter0
295 addi counter0, counter0, 1
296 srdi counter1, counter0, 32
298 addic counter0, counter0, 1
309 stw counter0, 0(counter)
/linux/drivers/gpu/drm/amd/include/ivsrcid/dcn/
H A Dirqsrcs_dcn_1_0.h78 #define DCN_1_0__SRCID__DCCG_PERFCOUNTER_INT0_STATUS 2 // DCCG perfmon counter0 interrupt DCCG_PERF…
84 #define DCN_1_0__SRCID__DMU_PERFCOUNTER_INT0_STATUS 3 // DMU perfmon counter0 interrupt DMU_PERFMON…
90 #define DCN_1_0__SRCID__DIO_PERFCOUNTER_INT0_STATUS 4 // DIO perfmon counter0 interrupt DIO_PERFMON…
123 #define DCN_1_0__SRCID__WB0_PERFCOUNTER_INT0_STATUS 6 // WB0 perfmon counter0 interrupt WB0_PERFMON…
372 #define DCN_1_0__SRCID__DCCG_PERFCOUNTER2_INT0_STATUS 0x11 // DCCG perfmon2 counter0 interrupt DCCG…
808 #define DCN_1_0__SRCID__DPP0_PERFCOUNTER_INT0_STATUS 0x24 // DPP0 perfmon counter0 interrupt DPP0_P…
832 #define DCN_1_0__SRCID__DPP1_PERFCOUNTER_INT0_STATUS 0x25 // DPP1 perfmon counter0 interrupt DPP1_P…
856 #define DCN_1_0__SRCID__DPP2_PERFCOUNTER_INT0_STATUS 0x26 // DPP2 perfmon counter0 interrupt DPP2_P…
880 #define DCN_1_0__SRCID__DPP3_PERFCOUNTER_INT0_STATUS 0x27 // DPP3 perfmon counter0 interrupt DPP3_P…
886 #define DCN_1_0__SRCID__DPP4_PERFCOUNTER_INT0_STATUS 0x28 // DPP4 perfmon counter0 interrupt DPP4_P…
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/linux/tools/counter/
H A Dcounter_example.c4 * The userspace application opens /dev/counter0, configures the
49 fd = open("/dev/counter0", O_RDWR); in main()
51 perror("Unable to open /dev/counter0"); in main()
/linux/drivers/watchdog/
H A Dni903x_wdt.c83 u8 control, counter0, counter1, counter2; in ni903x_wdd_get_timeleft() local
92 counter0 = inb(wdt->io_base + NIWD_COUNTER0); in ni903x_wdd_get_timeleft()
94 counter = (counter2 << 16) | (counter1 << 8) | counter0; in ni903x_wdd_get_timeleft()
/linux/drivers/rtc/
H A Drtc-au1xxx.c3 * Au1xxx counter0 (aka Time-Of-Year counter) RTC interface driver.
72 /* set counter0 tickrate to 1Hz if necessary */ in au1xtoy_rtc_probe()
/linux/drivers/gpu/drm/imagination/
H A Dpvr_rogue_mips.h219 /* Icache accesses in COUNTER0. */
224 /* Dcache accesses in COUNTER0. */
229 /* ITLB instruction accesses in COUNTER0. */
234 /* Instructions completed in COUNTER0. */
/linux/arch/mips/sibyte/common/
H A Dsb_tbprof.c102 "sd %0, 0x10($8);" /* write val to counter0 */ \
103 "sd %1, 0($8);" /* config counter0 for zclks*/ \
106 /* enable, counter0 */ \
117 "ld %0, 0x10($8);" /* write val to counter0 */ \
/linux/arch/arm/mm/
H A Dcache-l2x0-pmu.c30 * The L220/PL310 PMU has two equivalent counters, Counter1 and Counter0.
33 * Counter0.
34 * We ensure that idx 0 -> Counter0, and idx1 -> Counter1.
/linux/Documentation/devicetree/bindings/arm/
H A Darm,cci-400.yaml86 followed by counter0 overflow interrupt, counter1 overflow
/linux/arch/mips/sni/
H A Dtime.c91 /* Latch and spin until top byte of counter0 is zero */ in dosample()
/linux/drivers/perf/
H A Dfsl_imx9_ddr_perf.c41 * 64bit counter0 exclusively dedicated to counting cycles
212 /* counter0 cycles event */
H A Darm_smmuv3_pmu.c962 smmu_pmu->global_filter ? "Global(Counter0)" : in smmu_pmu_probe()