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/freebsd/sys/contrib/device-tree/Bindings/arm/
H A Dcoresight.txt1 * CoreSight Components:
3 CoreSight components are compliant with the ARM CoreSight architecture
8 sink. Each CoreSight component device should use these properties to describe
17 "arm,coresight-etb10", "arm,primecell";
20 "arm,coresight-tpiu", "arm,primecell";
26 "arm,coresight-tmc", "arm,primecell";
29 "arm,coresight-dynamic-funnel", "arm,primecell";
30 "arm,coresight-funnel", "arm,primecell"; (OBSOLETE. For
35 "arm,coresight-etm3x", "arm,primecell";
38 "arm,coresight-etm4x", "arm,primecell";
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H A Darm,coresight-dummy-sink.yaml4 $id: http://devicetree.org/schemas/arm/arm,coresight-dummy-sink.yaml#
7 title: ARM Coresight Dummy sink component
10 CoreSight components are compliant with the ARM CoreSight architecture
17 The Coresight dummy sink component is for the specific coresight sink devices
18 kernel don't have permission to access or configure, e.g., CoreSight EUD on
21 register it as Coresight sink device in kernel side, so that path can be
23 coresight link of AP processor. It provides Coresight AP
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H A Darm,coresight-dummy-source.yaml4 $id: http://devicetree.org/schemas/arm/arm,coresight-dummy-source.yaml#
7 title: ARM Coresight Dummy source component
10 CoreSight components are compliant with the ARM CoreSight architecture
17 The Coresight dummy source component is for the specific coresight source
19 there would be Coresight source trace components on sub-processor which
21 is needed to register them as Coresight source devices, so that paths can be
22 created in the driver. It provides Coresight API for operations on dummy
24 Coresight dumm
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H A Dcoresight-cti.yaml5 $id: http://devicetree.org/schemas/arm/coresight-cti.yaml#
8 title: ARM Coresight Cross Trigger Interface (CTI) device.
11 The CoreSight Embedded Cross Trigger (ECT) consists of CTI devices connected
12 to one or more CoreSight components and/or a CPU, with CTIs interconnected in
15 not part of the CoreSight graph described in the general CoreSight bindings
16 file coresight.txt.
38 indicate this feature (arm,coresight-cti-v8-arch).
49 between CTI and other CoreSight components.
51 Certain triggers between CoreSight devices and the CTI have specific types
53 constants defined in <dt-bindings/arm/coresight-cti-dt.h>
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H A Darm,coresight-etm.yaml4 $id: http://devicetree.org/schemas/arm/arm,coresight-etm.yaml#
7 title: Arm CoreSight Embedded Trace MacroCell
16 CoreSight components are compliant with the ARM CoreSight architecture
31 - arm,coresight-etm3x
32 - arm,coresight-etm4x
33 - arm,coresight-etm4x-sysreg
43 const: arm,coresight-etm4x-sysreg
56 - arm,coresight-etm3x
57 - arm,coresight-etm4x
61 const: arm,coresight-etm4x-sysreg
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H A Darm,coresight-cti.yaml5 $id: http://devicetree.org/schemas/arm/arm,coresight-cti.yaml#
8 title: ARM Coresight Cross Trigger Interface (CTI) device.
11 The CoreSight Embedded Cross Trigger (ECT) consists of CTI devices connected
12 to one or more CoreSight components and/or a CPU, with CTIs interconnected in
15 not part of the CoreSight graph.
37 indicate this feature (arm,coresight-cti-v8-arch).
48 between CTI and other CoreSight components.
50 Certain triggers between CoreSight devices and the CTI have specific types
52 constants defined in <dt-bindings/arm/coresight-cti-dt.h>
59 Note that some hardware trigger signals can be connected to non-CoreSight
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H A Dqcom,coresight-tpda.yaml5 $id: http://devicetree.org/schemas/arm/qcom,coresight-tpda.yaml#
23 Enable coresight sink first.
25 echo 1 > /sys/bus/coresight/devices/tmc_etf0/enable_sink
26 echo 1 > /sys/bus/coresight/devices/tpdm0/enable_source
27 echo 1 > /sys/bus/coresight/devices/tpdm0/integration_test
28 echo 2 > /sys/bus/coresight/devices/tpdm0/integration_test
30 The test data will be collected in the coresight sink which is enabled.
45 - qcom,coresight-tpda
54 - const: qcom,coresight-tpda
77 Output connections from the TPDA to legacy CoreSight trac
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H A Dete.yaml16 allows tracing the CPU execution. It overlaps with the CoreSight ETMv4
18 The trace generated by the ETE could be stored via legacy CoreSight
21 legacy CoreSight components, a node must be listed per instance, along
22 with any optional connection graph as per the coresight bindings.
23 See bindings/arm/coresight.txt.
39 Output connections from the ETE to legacy CoreSight trace bus.
43 description: Output connection from the ETE to legacy CoreSight Trace bus.
54 # An ETE node without legacy CoreSight connections
60 # An ETE node with legacy CoreSight connections
66 out-ports { /* legacy coresight connection */
H A Darm,coresight-dynamic-replicator.yaml4 $id: http://devicetree.org/schemas/arm/arm,coresight-dynamic-replicator.yaml#
7 title: Arm Coresight Programmable Trace Bus Replicator
16 CoreSight components are compliant with the ARM CoreSight architecture
23 The Coresight replicator splits a single trace stream into two trace streams
31 const: arm,coresight-dynamic-replicator
41 - const: arm,coresight-dynamic-replicator
72 description: Input connection from CoreSight Trace bus
80 description: Output connections to CoreSight Trace bus
96 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
H A Darm,coresight-dynamic-funnel.yaml4 $id: http://devicetree.org/schemas/arm/arm,coresight-dynamic-funnel.yaml#
7 title: Arm CoreSight Programmable Trace Bus Funnel
16 CoreSight components are compliant with the ARM CoreSight architecture
23 The Coresight funnel merges 2-8 trace sources into a single trace
31 const: arm,coresight-dynamic-funnel
41 - const: arm,coresight-dynamic-funnel
65 description: Input connections from CoreSight Trace bus
74 description: Output connection to CoreSight Trace bus
90 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
H A Darm,coresight-etb10.yaml4 $id: http://devicetree.org/schemas/arm/arm,coresight-etb10.yaml#
7 title: Arm CoreSight Embedded Trace Buffer
16 CoreSight components are compliant with the ARM CoreSight architecture
23 The CoreSight Embedded Trace Buffer stores traces in a dedicated SRAM that is
31 const: arm,coresight-etb10
41 - const: arm,coresight-etb10
66 description: Input connection from CoreSight Trace bus.
81 compatible = "arm,coresight-etb10", "arm,primecell";
H A Darm,coresight-tpiu.yaml4 $id: http://devicetree.org/schemas/arm/arm,coresight-tpiu.yaml#
7 title: Arm CoreSight Trace Port Interface Unit
16 CoreSight components are compliant with the ARM CoreSight architecture
23 The CoreSight Trace Port Interface Unit captures trace data from the trace bus
31 const: arm,coresight-tpiu
41 - const: arm,coresight-tpiu
66 description: Input connection from the CoreSight Trace bus.
81 compatible = "arm,coresight-tpiu", "arm,primecell";
H A Darm,embedded-trace-extension.yaml16 allows tracing the CPU execution. It overlaps with the CoreSight ETMv4
18 The trace generated by the ETE could be stored via legacy CoreSight
21 legacy CoreSight components, a node must be listed per instance, along
22 with any optional connection graph as per the coresight bindings.
41 Output connections from the ETE to legacy CoreSight trace bus.
45 description: Output connection from the ETE to legacy CoreSight Trace bus.
56 # An ETE node without legacy CoreSight connections
62 # An ETE node with legacy CoreSight connections
68 out-ports { /* legacy coresight connection */
H A Darm,coresight-static-funnel.yaml4 $id: http://devicetree.org/schemas/arm/arm,coresight-static-funnel.yaml#
7 title: Arm CoreSight Static Trace Bus Funnel
16 CoreSight components are compliant with the ARM CoreSight architecture
23 The Coresight static funnel merges 2-8 trace sources into a single trace
28 const: arm,coresight-static-funnel
38 description: Input connections from CoreSight Trace bus
47 description: Output connection to CoreSight Trace bus
64 compatible = "arm,coresight-static-funnel";
H A Darm,coresight-static-replicator.yaml4 $id: http://devicetree.org/schemas/arm/arm,coresight-static-replicator.yaml#
7 title: Arm CoreSight Static Trace Bus Replicator
16 CoreSight components are compliant with the ARM CoreSight architecture
23 The Coresight replicator splits a single trace stream into two trace streams
28 const: arm,coresight-static-replicator
39 description: Input connection from CoreSight Trace bus
47 description: Output connections to CoreSight Trace bus
64 compatible = "arm,coresight-static-replicator";
H A Darm,coresight-stm.yaml4 $id: http://devicetree.org/schemas/arm/arm,coresight-stm.yaml#
7 title: Arm CoreSight System Trace MacroCell
16 CoreSight components are compliant with the ARM CoreSight architecture
23 The STM is a trace source that is integrated into a CoreSight system, designed
33 const: arm,coresight-stm
43 - const: arm,coresight-stm
73 description: Output connection to the CoreSight Trace bus.
89 compatible = "arm,coresight-stm", "arm,primecell";
H A Darm,coresight-catu.yaml4 $id: http://devicetree.org/schemas/arm/arm,coresight-catu.yaml#
7 title: Arm Coresight Address Translation Unit (CATU)
16 CoreSight components are compliant with the ARM CoreSight architecture
23 The CoreSight Address Translation Unit (CATU) translates addresses between an
34 const: arm,coresight-catu
44 - const: arm,coresight-catu
73 description: AXI Slave connected to another Coresight component
89 compatible = "arm,coresight-catu", "arm,primecell";
H A Darm,coresight-cpu-debug.yaml4 $id: http://devicetree.org/schemas/arm/arm,coresight-cpu-debug.yaml#
7 title: CoreSight CPU Debug Component
16 CoreSight CPU debug component are compliant with the ARMv8 architecture
19 external debug, and it can be accessed from mmio region from Coresight and
29 const: arm,coresight-cpu-debug
39 - const: arm,coresight-cpu-debug
75 compatible = "arm,coresight-cpu-debug", "arm,primecell";
H A Darm,coresight-tmc.yaml4 $id: http://devicetree.org/schemas/arm/arm,coresight-tmc.yaml#
7 title: Arm CoreSight Trace Memory Controller
16 CoreSight components are compliant with the ARM CoreSight architecture
32 const: arm,coresight-tmc
42 - const: arm,coresight-tmc
91 description: Input connection from the CoreSight Trace bus.
116 compatible = "arm,coresight-tmc", "arm,primecell";
H A Dqcom,coresight-tpdm.yaml5 $id: http://devicetree.org/schemas/arm/qcom,coresight-tpdm.yaml#
31 - qcom,coresight-tpdm
40 - const: qcom,coresight-tpdm
73 Output connections from the TPDM to coresight funnel/TPDA.
78 description: Output connection from the TPDM to coresight
91 # minimum TPDM definition. TPDM connect to coresight TPDA.
94 compatible = "qcom,coresight-tpdm", "arm,primecell";
/freebsd/sys/contrib/device-tree/src/arm64/hisilicon/
H A Dhi6220-coresight.dtsi3 * dtsi file for Hisilicon Hi6220 coresight
14 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
39 compatible = "arm,coresight-tmc", "arm,primecell";
64 compatible = "arm,coresight-static-replicator";
100 compatible = "arm,coresight-tmc", "arm,primecell";
116 compatible = "arm,coresight-tpiu", "arm,primecell";
132 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
217 compatible = "arm,coresight-etm4x", "arm,primecell";
236 compatible = "arm,coresight-etm4x", "arm,primecell";
255 compatible = "arm,coresight-etm4x", "arm,primecell";
[all …]
H A Dhi3660-coresight.dtsi4 * dtsi for Hisilicon Hi3660 Coresight
15 compatible = "arm,coresight-etm4x", "arm,primecell";
32 compatible = "arm,coresight-etm4x", "arm,primecell";
49 compatible = "arm,coresight-etm4x", "arm,primecell";
66 compatible = "arm,coresight-etm4x", "arm,primecell";
83 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
132 compatible = "arm,coresight-tmc", "arm,primecell";
158 compatible = "arm,coresight-etm4x", "arm,primecell";
175 compatible = "arm,coresight-etm4x", "arm,primecell";
192 compatible = "arm,coresight-etm4x", "arm,primecell";
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/freebsd/sys/contrib/device-tree/src/arm/hisilicon/
H A Dhip04.dtsi272 compatible = "arm,coresight-etb10", "arm,primecell";
287 compatible = "arm,coresight-etb10", "arm,primecell";
302 compatible = "arm,coresight-etb10", "arm,primecell";
317 compatible = "arm,coresight-etb10", "arm,primecell";
332 compatible = "arm,coresight-tpiu", "arm,primecell";
350 compatible = "arm,coresight-static-replicator";
385 compatible = "arm,coresight-static-replicator";
420 compatible = "arm,coresight-static-replicator";
454 compatible = "arm,coresight-static-replicator";
485 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
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/freebsd/sys/contrib/device-tree/src/arm64/arm/
H A Djuno-base.dtsi117 * Juno TRMs specify the size for these coresight components as 64K.
122 compatible = "arm,coresight-tmc", "arm,primecell";
146 compatible = "arm,coresight-tpiu", "arm,primecell";
163 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
199 compatible = "arm,coresight-tmc", "arm,primecell";
217 compatible = "arm,coresight-stm", "arm,primecell";
234 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
269 compatible = "arm,coresight-cpu-debug", "arm,primecell";
278 compatible = "arm,coresight-etm4x", "arm,primecell";
294 compatible = "arm,coresight
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/freebsd/sys/arm64/coresight/
H A Dcoresight_funnel_fdt.c43 #include <arm64/coresight/coresight.h>
44 #include <arm64/coresight/coresight_funnel.h>
49 { "arm,coresight-funnel", HWTYPE_FUNNEL },
50 { "arm,coresight-static-funnel", HWTYPE_STATIC_FUNNEL },
67 device_set_desc(dev, "Coresight Funnel"); in funnel_fdt_probe()
70 device_set_desc(dev, "Coresight Static Funnel"); in funnel_fdt_probe()

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