Home
last modified time | relevance | path

Searched full:coreclock (Results 1 – 14 of 14) sorted by relevance

/linux/drivers/video/fbdev/kyro/
H A DSTG4000InitDevice.c118 u32 coreClock, in ProgramClock() argument
130 coreClock *= 100; /* in Hz */ in ProgramClock()
136 ulMinClock = coreClock - (coreClock >> 8); in ProgramClock()
137 ulMaxClock = coreClock + (coreClock >> 8); in ProgramClock()
140 ulScaleClockReq = coreClock >> STG4K3_PLL_SCALER; in ProgramClock()
179 ((coreClock > STG4K3_PLL_MAXR_VCO) in ProgramClock()
H A DSTG4000Interface.h37 extern u32 ProgramClock(u32 refClock, u32 coreClock, u32 *FOut, u32 *ROut, u32 *POut);
/linux/Documentation/devicetree/bindings/media/
H A Dcdns,csi2tx.txt47 <&coreclock>, <&coreclock>,
48 <&coreclock>, <&coreclock>;
H A Dcdns,csi2rx.yaml140 <&coreclock 8>, <&coreclock 9>,
141 <&coreclock 10>, <&coreclock 11>;
/linux/drivers/net/ethernet/microchip/sparx5/
H A Dsparx5_main.c480 enum sparx5_core_clockfreq freq = sparx5->coreclock; in sparx5_init_coreclock()
489 if (sparx5->coreclock == SPX5_CORE_CLOCK_DEFAULT) in sparx5_init_coreclock()
491 else if (sparx5->coreclock != SPX5_CORE_CLOCK_250MHZ) in sparx5_init_coreclock()
497 if (sparx5->coreclock == SPX5_CORE_CLOCK_DEFAULT) in sparx5_init_coreclock()
499 else if (sparx5->coreclock != SPX5_CORE_CLOCK_500MHZ) in sparx5_init_coreclock()
504 if (sparx5->coreclock == SPX5_CORE_CLOCK_DEFAULT) in sparx5_init_coreclock()
506 else if (sparx5->coreclock != SPX5_CORE_CLOCK_625MHZ) in sparx5_init_coreclock()
510 if (sparx5->coreclock == SPX5_CORE_CLOCK_DEFAULT) in sparx5_init_coreclock()
516 if (sparx5->coreclock == SPX5_CORE_CLOCK_DEFAULT) in sparx5_init_coreclock()
518 else if (sparx5->coreclock == SPX5_CORE_CLOCK_250MHZ) in sparx5_init_coreclock()
[all …]
H A Dsparx5_ptp.c35 switch (sparx5->coreclock) { in sparx5_ptp_get_1ppm()
60 switch (sparx5->coreclock) { in sparx5_ptp_get_nominal_value()
H A Dsparx5_calendar.c165 max_core_bw = sparx5_clk_to_bandwidth(sparx5->coreclock); in sparx5_config_auto_calendar()
285 clk_period_ps = sparx5_clk_period(sparx5->coreclock); in sparx5_dsm_calendar_calc()
H A Dsparx5_port.c472 u32 sys_clk = sparx5_clk_period(sparx5->coreclock); in sparx5_port_fifo_sz()
/linux/Documentation/devicetree/bindings/i3c/
H A Dcdns,i3c-master.yaml46 clocks = <&coreclock>, <&i3csysclock>;
H A Di3c.yaml161 clocks = <&coreclock>, <&i3csysclock>;
/linux/drivers/net/ethernet/microchip/sparx5/lan969x/
H A Dlan969x_calendar.c86 taxi_bw = (128 * 1000000) / sparx5_clk_period(sparx5->coreclock); in lan969x_dsm_calendar_calc()
/linux/arch/mips/kernel/
H A Didle.c76 * since coreclock (and the cp0 counter) stops upon executing it. Only an
/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dsmu8_hwmgr.c1623 level->coreClock = ps->levels[level_index].engineClock; in smu8_get_performance_level()
1628 level->coreClock = ps->levels[i].engineClock; in smu8_get_performance_level()
H A Dvega10_hwmgr.c5698 level->coreClock = vega10_ps->performance_levels[i].gfx_clock; in vega10_get_performance_level()