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Searched full:coreclk (Results 1 – 23 of 23) sorted by relevance

/linux/arch/arm/boot/dts/marvell/
H A Darmada-370-xp.dtsi56 clocks = <&coreclk 0>;
66 clocks = <&coreclk 0>;
76 clocks = <&coreclk 0>;
86 clocks = <&coreclk 0>;
96 clocks = <&coreclk 0>;
117 clocks = <&coreclk 0>;
126 clocks = <&coreclk 0>;
136 clocks = <&coreclk 0>;
146 clocks = <&coreclk 0>;
281 clocks = <&coreclk 0>;
[all …]
H A Darmada-38x.dtsi56 clocks = <&coreclk 0>;
66 clocks = <&coreclk 0>;
76 clocks = <&coreclk 0>;
86 clocks = <&coreclk 0>;
96 clocks = <&coreclk 0>;
131 clocks = <&coreclk 2>;
138 clocks = <&coreclk 2>;
156 clocks = <&coreclk 0>;
166 clocks = <&coreclk 0>;
176 clocks = <&coreclk 0>;
[all …]
H A Darmada-39x.dtsi93 clocks = <&coreclk 2>;
111 clocks = <&coreclk 0>;
121 clocks = <&coreclk 0>;
131 clocks = <&coreclk 0>;
141 clocks = <&coreclk 0>;
151 clocks = <&coreclk 0>;
161 clocks = <&coreclk 0>;
171 clocks = <&coreclk 0>;
181 clocks = <&coreclk 0>;
252 clocks = <&coreclk 0>;
[all …]
H A Darmada-375.dtsi89 clocks = <&coreclk 0>;
99 clocks = <&coreclk 0>;
109 clocks = <&coreclk 0>;
119 clocks = <&coreclk 0>;
129 clocks = <&coreclk 0>;
159 clocks = <&coreclk 2>;
221 clocks = <&coreclk 0>;
233 clocks = <&coreclk 0>;
243 clocks = <&coreclk 0>;
253 clocks = <&coreclk 0>;
[all …]
H A Darmada-xp.dtsi61 clocks = <&coreclk 0>;
73 clocks = <&coreclk 0>;
85 clocks = <&coreclk 0>;
89 coreclk: mvebu-sar@18230 { label
106 clocks = <&coreclk 1>;
255 clocks = <&coreclk 2>, <&refclk>;
261 clocks = <&coreclk 2>, <&refclk>;
H A Darmada-370.dtsi136 clocks = <&coreclk 0>;
151 clocks = <&coreclk 0>;
175 clocks = <&coreclk 0>;
179 coreclk: mvebu-sar@18230 { label
313 clocks = <&coreclk 2>;
318 clocks = <&coreclk 2>;
322 clocks = <&coreclk 0>;
326 clocks = <&coreclk 0>;
H A Darmada-xp-98dx3236.dtsi154 clocks = <&coreclk 0>;
162 clocks = <&coreclk 1>;
234 coreclk: mvebu-sar@f8204 { label
291 clocks = <&coreclk 2>, <&refclk>;
297 clocks = <&coreclk 2>, <&refclk>;
H A Darmada-xp-mv78230.dtsi234 clocks = <&coreclk 0>;
249 clocks = <&coreclk 0>;
H A Darmada-xp-mv78260.dtsi361 clocks = <&coreclk 0>;
376 clocks = <&coreclk 0>;
H A Darmada-xp-mv78460.dtsi410 clocks = <&coreclk 0>;
425 clocks = <&coreclk 0>;
H A Darmada-385-synology-ds116.dts75 clocks = <&coreclk 0>;
H A Darmada-370-synology-ds213j.dts80 clocks = <&coreclk 0>;
H A Darmada-xp-synology-ds414.dts86 clocks = <&coreclk 0>;
/linux/drivers/clk/sifive/
H A Dsifive-prci.c306 * sifive_prci_coreclksel_use_hfclk() - switch the CORECLK mux to output HFCLK
307 * @pd: struct __prci_data * for the PRCI containing the CORECLK mux reg
309 * Switch the CORECLK mux to the HFCLK input source; return once complete.
326 * sifive_prci_coreclksel_use_corepll() - switch the CORECLK mux to output
328 * @pd: struct __prci_data * for the PRCI containing the CORECLK mux reg
330 * Switch the CORECLK mux to the COREPLL output clock; return once complete.
347 * sifive_prci_coreclksel_use_final_corepll() - switch the CORECLK mux to output
349 * @pd: struct __prci_data * for the PRCI containing the CORECLK mux reg
351 * Switch the CORECLK mux to the final COREPLL output clock; return once
/linux/drivers/pci/controller/dwc/
H A Dpcie-visconti.c33 struct clk *coreclk; member
264 pcie->coreclk = devm_clk_get(dev, "core"); in visconti_get_resources()
265 if (IS_ERR(pcie->coreclk)) in visconti_get_resources()
266 return dev_err_probe(dev, PTR_ERR(pcie->coreclk), in visconti_get_resources()
/linux/Documentation/devicetree/bindings/clock/
H A Dfsl,qoriq-clock.yaml94 5 coreclk must be 0
105 A second input clock, called "coreclk", may be provided if
113 - const: coreclk
/linux/Documentation/devicetree/bindings/spi/
H A Dmarvell,orion-spi.yaml75 clocks = <&coreclk 0>;
99 clocks = <&coreclk 0>;
/linux/drivers/clk/
H A Dclk-qoriq.c92 struct clk *sysclk, *coreclk; member
1179 clk = input_clock_by_name(name, "coreclk"); in create_coreclk()
1184 * This indicates a mix of legacy nodes with the new coreclk in create_coreclk()
1186 * don't use the wrong input clock just because coreclk isn't in create_coreclk()
1220 if (cg->coreclk && idx != PLATFORM_PLL) { in create_one_pll()
1221 if (IS_ERR(cg->coreclk)) in create_one_pll()
1224 input = "cg-coreclk"; in create_one_pll()
1430 clk = cg->coreclk; in clockgen_clk_get()
1545 clockgen.coreclk = create_coreclk("cg-coreclk"); in _clockgen_init()
/linux/Documentation/devicetree/bindings/timer/
H A Dmrvl,mmp-timer.yaml43 clocks = <&coreclk 2>;
H A Dmarvell,armada-370-timer.yaml86 clocks = <&coreclk 2>, <&refclk>;
/linux/Documentation/devicetree/bindings/dma/
H A Dmarvell,orion-xor.yaml76 clocks = <&coreclk 0>;
/linux/sound/soc/fsl/
H A Dfsl_spdif.c113 * @coreclk: core clock for register access via DMA
139 struct clk *coreclk; member
1596 spdif_priv->coreclk = devm_clk_get(&pdev->dev, "core"); in fsl_spdif_probe()
1597 if (IS_ERR(spdif_priv->coreclk)) { in fsl_spdif_probe()
1599 return PTR_ERR(spdif_priv->coreclk); in fsl_spdif_probe()
1687 clk_disable_unprepare(spdif_priv->coreclk); in fsl_spdif_runtime_suspend()
1698 ret = clk_prepare_enable(spdif_priv->coreclk); in fsl_spdif_runtime_resume()
1737 clk_disable_unprepare(spdif_priv->coreclk); in fsl_spdif_runtime_resume()
/linux/arch/arm64/boot/dts/ti/
H A Dk3-am65-main.dtsi1131 icssg0_coreclk_mux: coreclk-mux@3c {
1302 icssg1_coreclk_mux: coreclk-mux@3c {
1473 icssg2_coreclk_mux: coreclk-mux@3c {