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Searched full:coreclk (Results 1 – 25 of 31) sorted by relevance

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/linux/arch/arm/boot/dts/marvell/
H A Darmada-370-xp.dtsi56 clocks = <&coreclk 0>;
66 clocks = <&coreclk 0>;
76 clocks = <&coreclk 0>;
86 clocks = <&coreclk 0>;
96 clocks = <&coreclk 0>;
117 clocks = <&coreclk 0>;
126 clocks = <&coreclk 0>;
136 clocks = <&coreclk 0>;
146 clocks = <&coreclk 0>;
281 clocks = <&coreclk 0>;
[all …]
H A Darmada-38x.dtsi56 clocks = <&coreclk 0>;
66 clocks = <&coreclk 0>;
76 clocks = <&coreclk 0>;
86 clocks = <&coreclk 0>;
96 clocks = <&coreclk 0>;
131 clocks = <&coreclk 2>;
138 clocks = <&coreclk 2>;
156 clocks = <&coreclk 0>;
166 clocks = <&coreclk 0>;
176 clocks = <&coreclk 0>;
[all …]
H A Darmada-39x.dtsi93 clocks = <&coreclk 2>;
111 clocks = <&coreclk 0>;
121 clocks = <&coreclk 0>;
131 clocks = <&coreclk 0>;
141 clocks = <&coreclk 0>;
151 clocks = <&coreclk 0>;
161 clocks = <&coreclk 0>;
171 clocks = <&coreclk 0>;
181 clocks = <&coreclk 0>;
252 clocks = <&coreclk 0>;
[all …]
H A Darmada-375.dtsi89 clocks = <&coreclk 0>;
99 clocks = <&coreclk 0>;
109 clocks = <&coreclk 0>;
119 clocks = <&coreclk 0>;
129 clocks = <&coreclk 0>;
159 clocks = <&coreclk 2>;
221 clocks = <&coreclk 0>;
233 clocks = <&coreclk 0>;
243 clocks = <&coreclk 0>;
253 clocks = <&coreclk 0>;
[all …]
H A Darmada-xp.dtsi61 clocks = <&coreclk 0>;
73 clocks = <&coreclk 0>;
85 clocks = <&coreclk 0>;
89 coreclk: mvebu-sar@18230 { label
106 clocks = <&coreclk 1>;
255 clocks = <&coreclk 2>, <&refclk>;
261 clocks = <&coreclk 2>, <&refclk>;
H A Darmada-370.dtsi136 clocks = <&coreclk 0>;
151 clocks = <&coreclk 0>;
175 clocks = <&coreclk 0>;
179 coreclk: mvebu-sar@18230 { label
313 clocks = <&coreclk 2>;
318 clocks = <&coreclk 2>;
322 clocks = <&coreclk 0>;
326 clocks = <&coreclk 0>;
H A Darmada-xp-98dx3236.dtsi154 clocks = <&coreclk 0>;
162 clocks = <&coreclk 1>;
234 coreclk: mvebu-sar@f8204 { label
291 clocks = <&coreclk 2>, <&refclk>;
297 clocks = <&coreclk 2>, <&refclk>;
H A Darmada-xp-mv78230.dtsi234 clocks = <&coreclk 0>;
249 clocks = <&coreclk 0>;
H A Darmada-xp-mv78260.dtsi361 clocks = <&coreclk 0>;
376 clocks = <&coreclk 0>;
H A Darmada-xp-mv78460.dtsi410 clocks = <&coreclk 0>;
425 clocks = <&coreclk 0>;
/linux/drivers/clk/sifive/
H A Dsifive-prci.c305 * sifive_prci_coreclksel_use_hfclk() - switch the CORECLK mux to output HFCLK
306 * @pd: struct __prci_data * for the PRCI containing the CORECLK mux reg
308 * Switch the CORECLK mux to the HFCLK input source; return once complete.
325 * sifive_prci_coreclksel_use_corepll() - switch the CORECLK mux to output
327 * @pd: struct __prci_data * for the PRCI containing the CORECLK mux reg
329 * Switch the CORECLK mux to the COREPLL output clock; return once complete.
346 * sifive_prci_coreclksel_use_final_corepll() - switch the CORECLK mux to output
348 * @pd: struct __prci_data * for the PRCI containing the CORECLK mux reg
350 * Switch the CORECLK mux to the final COREPLL output clock; return once
/linux/drivers/pci/controller/dwc/
H A Dpcie-visconti.c33 struct clk *coreclk; member
264 pcie->coreclk = devm_clk_get(dev, "core"); in visconti_get_resources()
265 if (IS_ERR(pcie->coreclk)) in visconti_get_resources()
266 return dev_err_probe(dev, PTR_ERR(pcie->coreclk), in visconti_get_resources()
/linux/Documentation/devicetree/bindings/timer/
H A Dmarvell,armada-370-xp-timer.txt33 clocks = <&coreclk 2>;
42 clocks = <&coreclk 2>, <&refclk>;
H A Dmrvl,mmp-timer.yaml43 clocks = <&coreclk 2>;
/linux/Documentation/devicetree/bindings/clock/
H A Dfsl,qoriq-clock.yaml94 5 coreclk must be 0
105 A second input clock, called "coreclk", may be provided if
113 - const: coreclk
H A Dmvebu-cpu-clock.txt16 clocks = <&coreclk 1>;
/linux/sound/soc/fsl/
H A Dfsl_esai.c38 * @coreclk: clock source to access register
64 struct clk *coreclk; member
984 esai_priv->coreclk = devm_clk_get(&pdev->dev, "core"); in fsl_esai_probe()
985 if (IS_ERR(esai_priv->coreclk)) { in fsl_esai_probe()
987 PTR_ERR(esai_priv->coreclk)); in fsl_esai_probe()
988 return PTR_ERR(esai_priv->coreclk); in fsl_esai_probe()
1132 ret = clk_prepare_enable(esai->coreclk); in fsl_esai_runtime_resume()
1169 clk_disable_unprepare(esai->coreclk); in fsl_esai_runtime_resume()
1186 clk_disable_unprepare(esai->coreclk); in fsl_esai_runtime_suspend()
H A Dfsl_spdif.c113 * @coreclk: core clock for register access via DMA
139 struct clk *coreclk; member
1596 spdif_priv->coreclk = devm_clk_get(&pdev->dev, "core"); in fsl_spdif_probe()
1597 if (IS_ERR(spdif_priv->coreclk)) { in fsl_spdif_probe()
1599 return PTR_ERR(spdif_priv->coreclk); in fsl_spdif_probe()
1687 clk_disable_unprepare(spdif_priv->coreclk); in fsl_spdif_runtime_suspend()
1698 ret = clk_prepare_enable(spdif_priv->coreclk); in fsl_spdif_runtime_resume()
1737 clk_disable_unprepare(spdif_priv->coreclk); in fsl_spdif_runtime_resume()
/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1012a.dtsi68 coreclk: coreclk { label
72 clock-output-names = "coreclk";
299 clocks = <&sysclk &coreclk>;
300 clock-names = "sysclk", "coreclk";
/linux/drivers/clk/
H A Dclk-qoriq.c92 struct clk *sysclk, *coreclk; member
1179 clk = input_clock_by_name(name, "coreclk"); in create_coreclk()
1184 * This indicates a mix of legacy nodes with the new coreclk in create_coreclk()
1186 * don't use the wrong input clock just because coreclk isn't in create_coreclk()
1220 if (cg->coreclk && idx != PLATFORM_PLL) { in create_one_pll()
1221 if (IS_ERR(cg->coreclk)) in create_one_pll()
1224 input = "cg-coreclk"; in create_one_pll()
1430 clk = cg->coreclk; in clockgen_clk_get()
1545 clockgen.coreclk = create_coreclk("cg-coreclk"); in _clockgen_init()
/linux/Documentation/devicetree/bindings/watchdog/
H A Dmoxa,moxart-watchdog.txt14 clocks = <&coreclk>;
/linux/Documentation/devicetree/bindings/dma/
H A Dmv-xor.txt32 clocks = <&coreclk 0>;
/linux/Documentation/devicetree/bindings/gpio/
H A Dgpio-mvebu.yaml145 clocks = <&coreclk 0>;
/linux/Documentation/devicetree/bindings/soc/ti/
H A Dti,pruss.yaml164 coreclk-mux@[a-f0-9]+$:
169 name "coreclk-mux".
/linux/drivers/soc/ti/
H A Dpruss.c396 "coreclk-mux", clks_np); in pruss_clk_init()
399 "failed to setup coreclk-mux\n"); in pruss_clk_init()

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