| /linux/arch/powerpc/boot/dts/fsl/ |
| H A D | p1020rdb-pc_camp_core0.dts | 3 * P1020 RDB-PC Core0 Device Tree Source in CAMP mode.
7 * This dts file allows core0 to have memory, l2, i2c, spi, gpio, tdm, dma, usb,
10 * Please note to add "-b 0" for core0's dts compiling.
|
| H A D | mpc8572ds_camp_core0.dts | 3 * MPC8572 DS Core0 Device Tree Source in CAMP mode.
7 * This dts file allows core0 to have memory, l2, i2c, dma1, global-util, eth0,
|
| /linux/Documentation/devicetree/bindings/media/ |
| H A D | qcom,sdm845-venus.yaml | 38 video-core0:
93 - video-core0
116 video-core0 {
|
| /linux/arch/arm64/boot/dts/amd/ |
| H A D | elba-16core.dtsi | 13 core0 { cpu = <&cpu0>; };
20 core0 { cpu = <&cpu4>; };
27 core0 { cpu = <&cpu8>; };
34 core0 { cpu = <&cpu12>; };
|
| H A D | amd-seattle-cpus.dtsi | 10 core0 {
18 core0 {
26 core0 {
34 core0 {
|
| /linux/arch/arm/boot/dts/intel/axm/ |
| H A D | axm5516-cpus.dtsi | 15 core0 {
29 core0 {
43 core0 {
57 core0 {
|
| /linux/arch/arm64/boot/dts/renesas/ |
| H A D | r8a78000.dtsi | 22 core0 {
37 core0 {
52 core0 {
67 core0 {
82 core0 {
97 core0 {
112 core0 {
127 core0 {
|
| /linux/arch/arm64/boot/dts/hisilicon/ |
| H A D | hip05.dtsi | 27 core0 {
41 core0 {
55 core0 {
69 core0 {
|
| H A D | hip07.dtsi | 27 core0 {
42 core0 {
57 core0 {
72 core0 {
87 core0 {
102 core0 {
117 core0 {
132 core0 {
147 core0 {
162 core0 {
[all …]
|
| /linux/arch/arm64/boot/dts/ti/ |
| H A D | k3-am654.dtsi | 16 core0 {
26 core0 {
|
| H A D | k3-j784s4.dtsi | 22 core0 {
40 core0 {
|
| H A D | k3-j7200.dtsi | 28 core0 {
146 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
|
| H A D | k3-j721s2.dtsi | 32 core0 {
153 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
|
| /linux/tools/perf/pmu-events/arch/arm64/freescale/imx94/sys/ |
| H A D | metrics.json | 179 "BriefDescription": "bytes of m33 core0 read from ddr",
187 "BriefDescription": "bytes of m33 core0 write to ddr",
195 "BriefDescription": "bytes of m7 core0 read from ddr",
203 "BriefDescription": "bytes of m7 core0 write to ddr",
|
| /linux/arch/arm64/boot/dts/exynos/ |
| H A D | exynos990.dtsi | 34 core0 {
52 core0 {
62 core0 {
|
| /linux/arch/arm/boot/dts/samsung/ |
| H A D | exynos5422-cpus.dtsi | 26 core0 {
41 core0 {
|
| H A D | exynos5420-cpus.dtsi | 27 core0 {
42 core0 {
|
| /linux/drivers/hwmon/ |
| H A D | k8temp.c | 172 scfg &= ~(SEL_PLACE | SEL_CORE); /* Select sensor 0, core0 */ in k8temp_probe()
188 scfg &= ~SEL_CORE; /* Select sensor 1, core0 */ in k8temp_probe()
|
| /linux/arch/arm64/boot/dts/apple/ |
| H A D | t600x-common.dtsi | 24 core0 {
33 core0 {
48 core0 {
|
| /linux/arch/arm/boot/dts/hisilicon/ |
| H A D | hip04.dtsi | 31 core0 {
45 core0 {
59 core0 {
73 core0 {
|
| /linux/drivers/remoteproc/ |
| H A D | xlnx_r5_remoteproc.c | 39 SINGLE_CPU_MODE = 2, /* core0 is held in reset and only core1 runs */
1162 * In split mode, r5 core0 will use 128k and r5 core1 will use another in zynqmp_r5_get_tcm_node()
1322 * 1) core0 enabled, core1 disabled in zynqmp_r5_cluster_init()
1323 * 2) core0 disabled, core1 enabled in zynqmp_r5_cluster_init()
1324 * 3) core0 and core1 both are enabled. in zynqmp_r5_cluster_init()
1328 * only use first child node and consider it as core0 in zynqmp_r5_cluster_init()
1336 dev_warn(dev, "Only r5 core0 will be used\n"); in zynqmp_r5_cluster_init()
|
| /linux/arch/arm/boot/dts/mediatek/ |
| H A D | mt8135.dtsi | 22 core0 {
31 core0 {
|
| /linux/arch/arm64/boot/dts/arm/ |
| H A D | juno-r1.dts | 42 core0 {
51 core0 {
|
| H A D | juno.dts | 41 core0 {
50 core0 {
|
| /linux/Documentation/devicetree/bindings/opp/ |
| H A D | opp-v2-kryo-cpu.yaml | 187 core0 {
197 core0 {
|