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/freebsd/sys/contrib/device-tree/Bindings/misc/
H A Daspeed,cvic.txt12 The AST2500 supports a SW generated interrupt
15 - reg: address and length of the register for the device.
16 - compatible: "aspeed,cvic" and one of:
17 "aspeed,ast2400-cvic"
19 "aspeed,ast2500-cvic"
21 - valid-sources: One cell, bitmap of supported sources for the implementation
24 - copro-sw-interrupts: List of interrupt numbers that can be used as
25 SW interrupts from the ARM to the coprocessor.
30 cvic: copro-interrupt-controller@1e6c2000 {
31 compatible = "aspeed,ast2500-cvic";
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H A Daspeed,ast2400-cvic.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/misc/aspeed,ast2400-cvic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Jeffery <andrew@codeconstruct.com.au>
13 The Aspeed AST2400 and AST2500 SoCs have a controller that provides interrupts
24 - enum:
25 - aspeed,ast2400-cvic
26 - aspeed,ast2500-cvic
27 - const: aspeed,cvic
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/freebsd/sys/contrib/device-tree/src/arm/aspeed/
H A Daspeed-g5.dtsi1 // SPDX-License-Identifier: GPL-2.0+
2 #include <dt-bindings/clock/aspeed-clock.h>
3 #include <dt-bindings/interrupt-controller/aspeed-scu-ic.h>
8 #address-cells = <1>;
9 #size-cells = <1>;
10 interrupt-parent = <&vic>;
36 #address-cells = <1>;
37 #size-cells = <0>;
40 compatible = "arm,arm1176jzf-s";
52 compatible = "simple-bus";
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