| /freebsd/sys/contrib/device-tree/Bindings/soc/rockchip/ |
| H A D | power_domain.txt | 6 Required properties for power domain controller:
7 - compatible: Should be one of the following.
8 "rockchip,px30-power-controller" - for PX30 SoCs.
9 "rockchip,rk3036-power-controller" - for RK3036 SoCs.
10 "rockchip,rk3066-power-controller" - for RK3066 SoCs.
11 "rockchip,rk3128-power-controller" - for RK3128 SoCs.
12 "rockchip,rk3188-power-controller" - for RK3188 SoCs.
13 "rockchip,rk3228-power-controller" - for RK3228 SoCs.
14 "rockchip,rk3288-power-controller" - for RK3288 SoCs.
15 "rockchip,rk3328-power-controller" - for RK3328 SoCs.
[all …]
|
| /freebsd/usr.sbin/mfiutil/ |
| H A D | mfiutil.8 | 40 .Op Fl t Ar type
45 .Op Fl t Ar type
52 .Op Fl t Ar type
57 .Op Fl t Ar type
62 .Op Fl t Ar type
72 .Op Fl t Ar type
77 .Op Fl t Ar type
82 .Op Fl t Ar type
89 .Op Fl t Ar type
96 .Op Fl t Ar type
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/gpio/ |
| H A D | gpio-altera.txt | 1 Altera GPIO controller bindings
4 - compatible:
5 - "altr,pio-1.0"
6 - reg: Physical base address and length of the controller's registers.
7 - #gpio-cells : Should be 2
8 - The first cell is the gpio offset number.
9 - The second cell is reserved and is currently unused.
10 - gpio-controller : Marks the device node as a GPIO controller.
11 - interrupt-controller: Mark the device node as an interrupt controller
12 - #interrupt-cells : Should be 2. The interrupt type is fixed in the hardware.
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/soundwire/ |
| H A D | qcom,sdw.txt | 1 Qualcomm SoundWire Controller Bindings
4 This binding describes the Qualcomm SoundWire Controller along with its
7 - compatible:
9 Value type: <stringlist>
10 Definition: must be "qcom,soundwire-v<MAJOR>.<MINOR>.<STEP>",
12 "qcom,soundwire-v1.3.0"
13 "qcom,soundwire-v1.5.0"
14 "qcom,soundwire-v1.5.1"
15 "qcom,soundwire-v1.6.0"
16 - reg:
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/powerpc/fsl/ |
| H A D | dcsr.txt | 21 - compatible
23 Value type: <string>
24 Definition: Must include "fsl,dcsr" and "simple-bus".
25 The DCSR space exists in the memory-mapped bus.
27 - #address-cells
29 Value type: <u32>
33 - #size-cells
35 Value type
[all...] |
| H A D | mpic.txt | 2 Freescale MPIC Interrupt Controller Node
6 The Freescale MPIC interrupt controller is found on all PowerQUICC
9 additional cells in the interrupt specifier defining interrupt type
14 - compatible
16 Value type: <string>
22 - reg
24 Value type: <prop-encoded-array>
29 - interrupt-controller
31 Value type: <empty>
33 controller
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/ |
| H A D | qcom,pdc.txt | 1 PDC interrupt controller
4 Power Domain Controller (PDC) that is on always-on domain. In addition to
6 interrupt controller that can be used to help detect edge low interrupts as
7 well detect interrupts when the GIC is non-operational.
9 GIC is parent interrupt controller at the highest level. Platform interrupt
10 controller PDC is next in hierarchy, followed by others. Drivers requiring
12 specify PDC as their interrupt controller and request the PDC port associated
17 - compatible:
19 Value type: <string>
20 Definition: Should contain "qcom,<soc>-pdc" and "qcom,pdc"
[all …]
|
| H A D | arm,gic-v3.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v3.yaml#
5 $schema: http://devicetree.org/meta-schema
[all...] |
| /freebsd/sys/contrib/device-tree/Bindings/pinctrl/ |
| H A D | qcom,sdm660-pinctrl.txt | 6 - compatible:
8 Value type: <string>
9 Definition: must be "qcom,sdm660-pinctrl" or
10 "qcom,sdm630-pinctrl".
12 - reg:
14 Value type: <prop-encoded-array>
18 - reg-names:
20 Value type: <stringlist>
24 - interrupts:
26 Value type: <prop-encoded-array>
[all …]
|
| H A D | qcom,mdm9615-pinctrl.txt | 6 - compatible:
8 Value type: <string>
9 Definition: must be "qcom,mdm9615-pinctrl"
11 - reg:
13 Value type: <prop-encoded-array>
16 - interrupts:
18 Value type: <prop-encoded-array>
21 - interrupt-controller:
23 Value type: <none>
24 Definition: identifies this node as an interrupt controller
[all …]
|
| H A D | mediatek,mt8188-pinctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8188-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek MT8188 Pin Controller
10 - Hui Liu <hui.liu@mediatek.com>
13 The MediaTek's MT8188 Pin controller is used to control SoC pins.
17 const: mediatek,mt8188-pinctrl
19 gpio-controller: true
21 '#gpio-cells':
[all …]
|
| H A D | qcom,apq8084-pinctrl.txt | 6 - compatible:
8 Value type: <string>
9 Definition: must be "qcom,apq8084-pinctrl"
11 - reg:
13 Value type: <prop-encoded-array>
16 - interrupts:
18 Value type: <prop-encoded-array>
21 - interrupt-controller:
23 Value type: <none>
24 Definition: identifies this node as an interrupt controller
[all …]
|
| H A D | qcom,ipq8074-pinctrl.txt | 6 - compatible:
8 Value type: <string>
9 Definition: must be "qcom,ipq8074-pinctrl"
11 - reg:
13 Value type: <prop-encoded-array>
16 - interrupts:
18 Value type: <prop-encoded-array>
21 - interrupt-controller:
23 Value type: <none>
24 Definition: identifies this node as an interrupt controller
[all …]
|
| H A D | qcom,msm8960-pinctrl.txt | 6 - compatible:
8 Value type: <string>
9 Definition: must be "qcom,msm8960-pinctrl"
11 - reg:
13 Value type: <prop-encoded-array>
16 - interrupts:
18 Value type: <prop-encoded-array>
21 - interrupt-controller:
23 Value type: <none>
24 Definition: identifies this node as an interrupt controller
[all …]
|
| H A D | qcom,msm8976-pinctrl.txt | 6 - compatible:
8 Value type: <string>
9 Definition: must be "qcom,msm8976-pinctrl"
11 - reg:
13 Value type: <prop-encoded-array>
16 - interrupts:
18 Value type: <prop-encoded-array>
21 - interrupt-controller:
23 Value type: <none>
24 Definition: identifies this node as an interrupt controller
[all …]
|
| H A D | qcom,sdm845-pinctrl.txt | 6 - compatible:
8 Value type: <string>
9 Definition: must be "qcom,sdm845-pinctrl"
11 - reg:
13 Value type: <prop-encoded-array>
16 - interrupts:
18 Value type: <prop-encoded-array>
21 - interrupt-controller:
23 Value type: <none>
24 Definition: identifies this node as an interrupt controller
[all …]
|
| H A D | mediatek,mt8186-pinctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8186-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek MT8186 Pin Controller
10 - Sean Wang <sean.wang@mediatek.com>
13 The MediaTek's MT8186 Pin controller is used to control SoC pins.
17 const: mediatek,mt8186-pinctrl
19 gpio-controller: true
21 '#gpio-cells':
[all …]
|
| H A D | pinctrl-mt8186.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/pinctrl-mt8186.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mediatek MT8186 Pin Controller
10 - Sean Wang <sean.wang@mediatek.com>
13 The Mediatek's Pin controller is used to control SoC pins.
17 const: mediatek,mt8186-pinctrl
19 gpio-controller: true
21 '#gpio-cells':
[all …]
|
| H A D | mediatek,mt8195-pinctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8195-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek MT8195 Pin Controller
10 - Sean Wang <sean.wang@mediatek.com>
13 The MediaTek's MT8195 Pin controller is used to control SoC pins.
17 const: mediatek,mt8195-pinctrl
19 gpio-controller: true
21 '#gpio-cells':
[all …]
|
| H A D | pinctrl-mt8195.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/pinctrl-mt8195.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mediatek MT8195 Pin Controller
10 - Sean Wang <sean.wang@mediatek.com>
13 The Mediatek's Pin controller is used to control SoC pins.
17 const: mediatek,mt8195-pinctrl
19 gpio-controller: true
21 '#gpio-cells':
[all …]
|
| H A D | qcom,sc7180-pinctrl.txt | 6 - compatible:
8 Value type: <string>
9 Definition: must be "qcom,sc7180-pinctrl"
11 - reg:
13 Value type: <prop-encoded-array>
17 - reg-names:
19 Value type: <prop-encoded-array>
23 - interrupts:
25 Value type: <prop-encoded-array>
28 - interrupt-controller:
[all …]
|
| H A D | qcom,sm8150-pinctrl.txt | 6 - compatible:
8 Value type: <string>
9 Definition: must be "qcom,sm8150-pinctrl"
11 - reg:
13 Value type: <prop-encoded-array>
17 - reg-names:
19 Value type: <prop-encoded-array>
23 - interrupts:
25 Value type: <prop-encoded-array>
28 - interrupt-controller:
[all …]
|
| H A D | mediatek,mt6795-pinctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt6795-pinctr
[all...] |
| H A D | mediatek,pinctrl-mt6795.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,pinctrl-mt6795.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mediatek MT6795 Pin Controller
10 - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
11 - Sean Wang <sean.wang@kernel.org>
14 The Mediatek's Pin controller is used to control SoC pins.
18 const: mediatek,mt6795-pinctrl
20 gpio-controller: true
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/arm/keystone/ |
| H A D | ti,sci.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schema
[all...] |