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/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Dpci-msi.txt16 MSIs may be distinguished in part through the use of sideband data accompanying
17 writes. In the case of PCI devices, this sideband data may be derived from the
19 controllers it can address, and the sideband data that will be associated with
23 Documentation/devicetree/bindings/interrupt-controller/msi.txt.
30 -------------------
32 - msi-map: Maps a Requester ID to an MSI controller and associated
33 msi-specifier data. The property is an arbitrary number of tuples of
34 (rid-base,msi-controller,msi-base,length), where:
36 * rid-base is a single cell describing the first RID matched by the entry.
38 * msi-controller is a single phandle to an MSI controller
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/freebsd/sbin/nvmecontrol/
H A Dnvmecontrol.83 .\" Copyright (c) 2018-2019 Alexander Motin <mav@FreeBSD.org>
26 .\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
51 .Aq Ar device-id | Ar namespace-id
59 .Aq Ar namespace-id
62 .Aq Ar device-id
67 .Op Fl v Ar vendor-string
72 .Aq Ar device-id | Ar namespace-id
75 .Aq Ar device-id
78 .Aq Ar device-id
83 .Aq Ar device-id
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/freebsd/sys/contrib/device-tree/Bindings/gpio/
H A Dgpio-ep9301.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/gpio-ep9301.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: EP93xx GPIO controller
10 - Linus Walleij <linus.walleij@linaro.org>
11 - Bartosz Golaszewski <brgl@bgdev.pl>
12 - Nikita Shubin <nikita.shubin@maquefel.me>
17 - const: cirrus,ep9301-gpio
18 - items:
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/freebsd/lib/libnvmf/
H A Dlibnvmf.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2022-2024 Chelsio Communications, Inc.
24 * Parameters shared by all queue-pairs of an association. Note that
30 bool dynamic_controller_model; /* Controller only */
31 uint16_t max_admin_qsize; /* Controller only */
32 uint32_t max_io_qsize; /* Controller only, 0 for discovery */
35 uint8_t pda; /* Tx-side PDA. */
39 uint32_t maxh2cdata; /* Controller only */
54 /* Transport-independent APIs. */
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/freebsd/share/doc/papers/diskperf/
H A Dequip.ms22 .\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
38 The DEC UDA50 disk controller was interfaced to two DEC RA81
43 their controller, but we did not have time to test this device.
49 DEC UDA50 disk controller
51 This is a new controller design which is part of a larger, long range
58 intelligent controller than previous interfaces like the RH750 or
66 are determined by the controller.
69 Where multiple drives are attached to a single controller,
72 data transfers from multiple drives.
74 The UDA50 is a UNIBUS implementation of a DSA controller.
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/freebsd/share/man/man4/
H A Dng_hci.41 .\" Copyright (c) 2001-2002 Maksim Yevmenkin <m_evmenkin@yahoo.com>
19 .\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
32 .Nd Netgraph node type that is also a Bluetooth Host Controller Interface
40 node type is a Netgraph node type that implements Bluetooth Host Controller
44 Bluetooth is a short-range radio link intended to replace the cable(s)
50 asynchronous data channel, up to three simultaneous synchronous voice
51 channels, or a channel which simultaneously supports asynchronous data
59 The Bluetooth system provides a point-to-point connection (only two
60 Bluetooth units involved), or a point-to-multipoint connection.
61 In the point-to-multipoint connection,
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/freebsd/sys/contrib/device-tree/Bindings/media/
H A Dmicrochip,csi2dc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip CSI2 Demux Controller (CSI2DC)
10 - Eugen Hristev <eugen.hristev@microchip.com>
13 CSI2DC - Camera Serial Interface 2 Demux Controller
15 CSI2DC is a hardware block that receives incoming data from either from an
17 It filters IDI packets based on their data type and virtual channel
20 controller.
22 CSI2DC can act a simple bypass bridge if the incoming data is coming from
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/freebsd/sys/contrib/device-tree/Bindings/soundwire/
H A Dqcom,sdw.txt1 Qualcomm SoundWire Controller Bindings
4 This binding describes the Qualcomm SoundWire Controller along with its
7 - compatible:
10 Definition: must be "qcom,soundwire-v<MAJOR>.<MINOR>.<STEP>",
12 "qcom,soundwire-v1.3.0"
13 "qcom,soundwire-v1.5.0"
14 "qcom,soundwire-v1.5.1"
15 "qcom,soundwire-v1.6.0"
16 - reg:
18 Value type: <prop-encoded-array>
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/freebsd/sys/dev/nvmf/
H A Dnvmf_transport.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2022-2024 Chelsio Communications, Inc.
12 * Interface used by the Fabrics host (initiator) and controller
13 * (target) to send and receive capsules and associated data.
42 * parameter is the amount of data transferred. The last parameter is
43 * an error value which is non-zero if the request did not complete
58 bool controller, const nvlist_t *params,
64 * Capsules are either commands (host -> controller) or responses
65 * (controller -> host). A data buffer may be associated with a
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/freebsd/sys/dev/isci/scil/
H A Dscic_sgpio.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause OR GPL-2.0
9 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
22 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
28 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
49 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
112 * @param[in] SCI_CONTROLLER_HANDLE_T controller
113 * @param]in] vendor_specific_sequence - Vendor specific sequence set in the
118 SCI_CONTROLLER_HANDLE_T controller,
127 * @param[in] SCI_CONTROLLER_HANDLE_T controller
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H A Dscu_bios_definitions.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause OR GPL-2.0
9 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
22 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
28 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
49 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
64 * stand-alone where the library is excluded. By excluding
85 // For Intel Storage Controller Unit OEM Block
124 * contains valid OEM Parameter data. The value must be set to
126 * stands for Intel Storage Controller Unit OEM Block.
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H A Dscic_user_callback.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause OR GPL-2.0
9 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
22 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
28 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
49 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
77 * exclusive manner from the controller completion handler
80 * @param[in] controller This parameter specifies the controller with
93 SCI_CONTROLLER_HANDLE_T controller,
101 * @param[in] controller This parameter specifies the controller with
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H A Dscif_user_callback.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause OR GPL-2.0
9 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
22 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
28 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
49 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
81 * exclusive manner from the controller completion handler
86 * @param[in] controller This parameter specifies the controller with
97 SCI_CONTROLLER_HANDLE_T controller,
105 * @param[in] controller This parameter specifies the controller with
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/freebsd/sys/contrib/alpine-hal/
H A Dal_hal_udma_iofic.h1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
30 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
38 * @defgroup group_udma_interrupts UDMA I/O Fabric Interrupt Controller
44 * @brief C Header file for programming the interrupt controller that found
45 * in UDMA based units. These APIs rely and use some the Interrupt controller
56 /* *INDENT-OFF* */
60 /* *INDENT-ON* */
69 AL_IOFIC_MODE_LEGACY, /**< level-sensitive interrupt wire */
70 AL_IOFIC_MODE_MSIX_PER_Q, /**< per UDMA queue MSI-X interrupt */
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/freebsd/share/misc/
H A Dpci_vendors5 # Date: 2025-03-09 03:15:02
8 # the PCI ID Project at https://pci-ids.ucw.cz/.
10 # New data are always welcome, especially if they are accurate. If you have
14 # (version 2 or higher) or the 3-clause BSD License.
16 # The database is a compilation of factual data, and as such the copyright
25 # device device_name <-- single tab
26 # subvendor subdevice subsystem_name <-- two tabs
30 # This is a relabelled RTL-8139
31 8139 AT-2500TX V3 Ethernet
33 7a00 Hyper Transport Bridge Controller
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/freebsd/sys/contrib/device-tree/Bindings/auxdisplay/
H A Dhit,hd44780.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Hitachi HD44780 Character LCD Controller
10 - Geert Uytterhoeven <geert@linux-m68k.org>
13 The Hitachi HD44780 Character LCD Controller is commonly used on character
15 interface, which can be used in either 4-bit or 8-bit mode. By using a
24 data-gpios:
26 GPIO pins connected to the data signal lines DB0-DB7 (8-bit mode) or
27 DB4-DB7 (4-bit mode) of the LCD Controller's bus interface.
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/freebsd/sys/dev/sdhci/
H A Dsdhci.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 /* Controller doesn't honor resets unless we touch the clock register */
38 /* Controller really supports DMA */
40 /* Controller has unusable DMA engine */
42 /* Controller doesn't like to be reset when there is no card inserted. */
44 /* Controller has flaky internal state so reset it on each ios change */
46 /* Controller can only DMA chunk sizes that are a multiple of 32 bits */
48 /* Controller needs to be reset after each request to stay stable */
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/freebsd/stand/efi/include/
H A Defipciio.h3 and DMA interfaces that a driver uses to access its PCI controller.
5 Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
9 http://opensource.org/licenses/bsd-license.php
56 #define EFI_PCI_IO_ATTRIBUTE_ISA_MOTHERBOARD_IO 0x0001 ///< I/O cycles 0x0000-0x00FF (10 bit dec…
57 #define EFI_PCI_IO_ATTRIBUTE_ISA_IO 0x0002 ///< I/O cycles 0x0100-0x03FF or greater …
59 #define EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY 0x0008 ///< MEM cycles 0xA0000-0xBFFFF (24 bit d…
60 #define EFI_PCI_IO_ATTRIBUTE_VGA_IO 0x0010 ///< I/O cycles 0x3B0-0x3BB and 0x3C0-0x3…
61 #define EFI_PCI_IO_ATTRIBUTE_IDE_PRIMARY_IO 0x0020 ///< I/O cycles 0x1F0-0x1F7, 0x3F6, 0x3F7…
62 #define EFI_PCI_IO_ATTRIBUTE_IDE_SECONDARY_IO 0x0040 ///< I/O cycles 0x170-0x177, 0x376, 0x377…
69 #define EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE 0x2000 ///< Clear for an add-in PCI Device
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/freebsd/sys/contrib/device-tree/Bindings/mtd/
H A Dqcom_nandc.txt1 * Qualcomm NAND controller
4 - compatible: must be one of the following:
5 * "qcom,ipq806x-nand" - for EBI2 NAND controller being used in IPQ806x
7 * "qcom,ipq4019-nand" - for QPIC NAND controller v1.4.0 being used in
9 * "qcom,ipq6018-nand" - for QPIC NAND controller v1.5.0 being used in
11 * "qcom,ipq8074-nand" - for QPIC NAND controller v1.5.0 being used in
13 * "qcom,sdx55-nand" - for QPIC NAND controller v2.0.0 being used in
16 - reg: MMIO address range
17 - clocks: must contain core clock and always on clock
18 - clock-names: must contain "core" for the core clock and "aon" for the
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/freebsd/sys/contrib/device-tree/Bindings/dma/
H A Dsnps,dma-spear1340.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/dma/snps,dma-spear1340.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys Designware DMA Controller
10 - Viresh Kumar <vireshk@kernel.org>
11 - Andy Shevchenko <andriy.shevchenko@linux.intel.com>
14 - $ref: dma-controller.yaml#
19 - const: snps,dma-spear1340
20 - items:
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/freebsd/sys/contrib/device-tree/src/arm/cirrus/
H A Dep93xx.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/leds/common.h>
7 #include <dt-bindings/input/input.h>
8 #include <dt-bindings/clock/cirrus,ep9301-syscon.h>
11 compatible = "simple-bus";
13 #address-cells = <1>;
14 #size-cells = <1>;
17 compatible = "cirrus,ep9301-syscon", "syscon";
20 #clock-cells = <1>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/thermal/
H A Dmediatek-thermal.txt3 This describes the device tree binding for the Mediatek thermal controller
4 which measures the on-SoC temperatures. This device does not have its own ADC,
11 - compatible:
12 - "mediatek,mt8173-thermal" : For MT8173 family of SoCs
13 - "mediatek,mt2701-thermal" : For MT2701 family of SoCs
14 - "mediatek,mt2712-thermal" : For MT2712 family of SoCs
15 - "mediatek,mt7622-thermal" : For MT7622 SoC
16 - "mediatek,mt7981-thermal", "mediatek,mt7986-thermal" : For MT7981 SoC
17 - "mediatek,mt7986-thermal" : For MT7986 SoC
18 - "mediatek,mt8183-thermal" : For MT8183 family of SoCs
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/freebsd/sys/dev/mlx/
H A Dmlxvar.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * 0 - quiet, only emit warnings
35 * 1 - noisy, emit major function points and things done
36 * 2 - extremely noisy, emit trace items in loops, etc.
47 * Regardless of the actual capacity of the controller, we will allocate space
49 * 128k maximum transfer assuming 4k page size and non-optimal alignment), but
61 * Structure describing a System Drive as attached to the controller.
80 * Per-command control structure.
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/freebsd/sys/contrib/device-tree/Bindings/soc/mediatek/
H A Dmtk-svs.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/mediatek/mtk-sv
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/freebsd/sys/contrib/device-tree/Bindings/net/can/
H A Dcc770.txt1 Memory mapped Bosch CC770 and Intel AN82527 CAN controller
3 Note: The CC770 is a CAN controller from Bosch, which is 100%
8 - compatible : should be "bosch,cc770" for the CC770 and "intc,82527"
11 - reg : should specify the chip select, address offset and size required
12 to map the registers of the controller. The size is usually 0x80.
14 - interrupts : property with a value describing the interrupt source
15 (number and sensitivity) required for the controller.
19 - bosch,external-clock-frequenc
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