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/linux/drivers/iio/multiplexer/
H A Diio-mux.c1 // SPDX-License-Identifier: GPL-2.0
32 struct mux_control *control; member
33 struct iio_channel *parent; member
42 struct mux_child *child = &mux->child[idx]; in iio_mux_select()
43 struct iio_chan_spec const *chan = &mux->chan[idx]; in iio_mux_select()
47 ret = mux_control_select_delay(mux->control, chan->channel, in iio_mux_select()
48 mux->delay_us); in iio_mux_select()
50 mux->cached_state = -1; in iio_mux_select()
54 if (mux->cached_state == chan->channel) in iio_mux_select()
57 if (chan->ext_info) { in iio_mux_select()
[all …]
/linux/Documentation/devicetree/bindings/mux/
H A Dreg-mux.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mux/reg-mux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic register bitfield-based multiplexer controller
10 - Peter Rosin <peda@axentia.se>
13 Define register bitfields to be used to control multiplexers. The parent
19 - reg-mux # parent device of mux controller is not syscon device
20 - mmio-mux # parent device of mux controller is syscon device
24 '#mux-control-cells':
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H A Dmux-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mux/mux-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Peter Rosin <peda@axentia.se>
14 that uses the mux controller. Thus, a mux controller can possibly control
17 control several multiplexers for a single consumer.
20 space is a simple zero-based enumeration. I.e. 0-1 for a 2-way multiplexer,
21 0-7 for an 8-way multiplexer, etc.
25 --------------------
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H A Dgpio-mux.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mux/gpio-mux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: GPIO-based multiplexer controller
10 - Peter Rosin <peda@axentia.se>
13 Define what GPIO pins are used to control a multiplexer. Or several
14 multiplexers, if the same pins control more than one multiplexer.
22 const: gpio-mux
24 mux-gpios:
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/linux/include/linux/firmware/imx/svc/
H A Dpm.h1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Copyright 2017-2018 NXP
8 * control, clock control, reset control, and wake-up event control.
56 #define IMX_SC_PM_PW_MODE_LP 2 /* Power in low-power */
77 * Defines for SC PM CLK Parent
79 #define IMX_SC_PM_PARENT_XTAL 0 /* Parent is XTAL. */
80 #define IMX_SC_PM_PARENT_PLL0 1 /* Parent is PLL0 */
81 #define IMX_SC_PM_PARENT_PLL1 2 /* Parent is PLL1 or PLL0/2 */
82 #define IMX_SC_PM_PARENT_PLL2 3 /* Parent in PLL2 or PLL0/4 */
83 #define IMX_SC_PM_PARENT_BYPS 4 /* Parent is a bypass clock. */
/linux/include/linux/
H A Dpowercap.h1 /* SPDX-License-Identifier: GPL-2.0-only */
24 * struct powercap_control_type_ops - Define control type callbacks
25 * @set_enable: Enable/Disable whole control type.
32 * control type is closed. So it is safe to free data
33 * structure associated with this control type.
35 * for the control type.
37 * This structure defines control type callbacks to be implemented by client
47 * struct powercap_control_type - Defines a powercap control_type
52 * @lock: mutex for control type
58 * @node: linked-list node
[all …]
/linux/drivers/acpi/acpica/
H A Dpsparse.c1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
4 * Module Name: psparse - Parser top level AML parse routines
6 * Copyright (C) 2000 - 2025, Intel Corp.
34 * PARAMETERS: opcode - An AML opcode
44 /* Extended (2-byte) opcode if > 255 */ in acpi_ps_get_opcode_size()
59 * PARAMETERS: parser_state - A parser state object
72 aml = parser_state->aml; in acpi_ps_peek_opcode()
90 * PARAMETERS: walk_state - Current State
91 * op - Op to complete
121 if (((walk_state->parse_flags & ACPI_PARSE_TREE_MASK) != in acpi_ps_complete_this_op()
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/linux/drivers/regulator/
H A Dtps65090-regulator.c1 // SPDX-License-Identifier: GPL-2.0-only
33 * struct tps65090_regulator - Per-regulator data for a tps65090 regulator
54 * tps65090_reg_set_overcurrent_wait - Setup overcurrent wait
62 * Return: 0 if no error, non-zero if there was an error writing the register.
69 ret = regmap_update_bits(rdev->regmap, rdev->desc->enable_reg, in tps65090_reg_set_overcurrent_wait()
71 ri->overcurrent_wait << CTRL_WT_BIT); in tps65090_reg_set_overcurrent_wait()
73 dev_err(&rdev->dev, "Error updating overcurrent wait %#x\n", in tps65090_reg_set_overcurrent_wait()
74 rdev->desc->enable_reg); in tps65090_reg_set_overcurrent_wait()
81 * tps65090_try_enable_fet - Try to enable a FET
85 * Return: 0 if ok, -ENOTRECOVERABLE if the FET power good bit did not get
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/linux/drivers/hid/
H A Dhid-roccat-koneplus.c1 // SPDX-License-Identifier: GPL-2.0-or-later
13 * and functionality and without the non-standard behaviours the Kone had.
22 #include <linux/hid-roccat.h>
23 #include "hid-ids.h"
24 #include "hid-roccat-common.h"
25 #include "hid-roccat-koneplus.h"
32 koneplus->actual_profile = new_profile; in koneplus_profile_activated()
38 struct roccat_common2_control control; in koneplus_send_control() local
43 return -EINVAL; in koneplus_send_control()
45 control.command = ROCCAT_COMMON_COMMAND_CONTROL; in koneplus_send_control()
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H A Dhid-roccat-kovaplus.c1 // SPDX-License-Identifier: GPL-2.0-or-later
20 #include <linux/hid-roccat.h>
21 #include "hid-ids.h"
22 #include "hid-roccat-common.h"
23 #include "hid-roccat-kovaplus.h"
35 if (new_profile_index >= ARRAY_SIZE(kovaplus->profile_settings)) in kovaplus_profile_activated()
37 kovaplus->actual_profile = new_profile_index; in kovaplus_profile_activated()
38 kovaplus->actual_cpi = kovaplus->profile_settings[new_profile_index].cpi_startup_level; in kovaplus_profile_activated()
39 kovaplus->actual_x_sensitivity = kovaplus->profile_settings[new_profile_index].sensitivity_x; in kovaplus_profile_activated()
40 kovaplus->actual_y_sensitivity = kovaplus->profile_settings[new_profile_index].sensitivity_y; in kovaplus_profile_activated()
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H A Dhid-roccat-pyra.c1 // SPDX-License-Identifier: GPL-2.0-or-later
22 #include <linux/hid-roccat.h>
23 #include "hid-ids.h"
24 #include "hid-roccat-common.h"
25 #include "hid-roccat-pyra.h"
32 if (new_profile >= ARRAY_SIZE(pyra->profile_settings)) in profile_activated()
34 pyra->actual_profile = new_profile; in profile_activated()
35 pyra->actual_cpi = pyra->profile_settings[pyra->actual_profile].y_cpi; in profile_activated()
41 struct roccat_common2_control control; in pyra_send_control() local
46 return -EINVAL; in pyra_send_control()
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H A Dhid-roccat-common.c1 // SPDX-License-Identifier: GPL-2.0-or-later
14 #include "hid-roccat-common.h"
29 return -ENOMEM; in roccat_common2_receive()
39 return ((len < 0) ? len : ((len != size) ? -EIO : 0)); in roccat_common2_receive()
51 return -ENOMEM; in roccat_common2_send()
60 return ((len < 0) ? len : ((len != size) ? -EIO : 0)); in roccat_common2_send()
75 struct roccat_common2_control control; in roccat_common2_receive_control_status() local
81 &control, sizeof(struct roccat_common2_control)); in roccat_common2_receive_control_status()
86 switch (control.value) { in roccat_common2_receive_control_status()
95 return -EINVAL; in roccat_common2_receive_control_status()
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/linux/drivers/clk/bcm/
H A Dclk-kona-setup.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include "clk-kona.h"
13 #define selector_clear_exists(sel) ((sel)->width = 0)
20 struct ccu_policy *ccu_policy = &ccu->policy; in ccu_data_offsets_valid()
23 limit = ccu->range - sizeof(u32); in ccu_data_offsets_valid()
26 if (ccu_policy->enable.offset > limit) { in ccu_data_offsets_valid()
29 ccu->name, ccu_policy->enable.offset, limit); in ccu_data_offsets_valid()
32 if (ccu_policy->control.offset > limit) { in ccu_data_offsets_valid()
33 pr_err("%s: bad policy control offset for %s " in ccu_data_offsets_valid()
35 ccu->name, ccu_policy->control.offset, limit); in ccu_data_offsets_valid()
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H A Dclk-kona.h1 /* SPDX-License-Identifier: GPL-2.0-only */
16 #include <linux/clk-provider.h>
20 /* The common clock framework uses u8 to represent a parent index */
24 #define BAD_CLK_NAME ((const char *)-1)
33 #define FLAG_SET(obj, type, flag) ((obj)->flags |= FLAG(type, flag))
34 #define FLAG_CLEAR(obj, type, flag) ((obj)->flags &= ~(FLAG(type, flag)))
35 #define FLAG_FLIP(obj, type, flag) ((obj)->flags ^= FLAG(type, flag))
36 #define FLAG_TEST(obj, type, flag) (!!((obj)->flags & FLAG(type, flag)))
40 #define ccu_policy_exists(ccu_policy) ((ccu_policy)->enable.offset != 0)
44 #define policy_exists(policy) ((policy)->offset != 0)
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H A Dclk-kona.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include "clk-kona.h"
12 #include <linux/clk-provider.h>
28 /* Produces a mask of set bits covering a range of a 32-bit value */
31 return ((1 << width) - 1) << shift; in bitfield_mask()
53 return (u64)reg_div + ((u64)1 << div->u.s.frac_width); in scaled_div_value()
61 return (u64)div->u.fixed; in scaled_div_min()
72 return (u64)div->u.fixed; in scaled_div_max()
74 reg_div = ((u32)1 << div->u.s.width) - 1; in scaled_div_max()
89 return (u32)(scaled_div - ((u64)1 << div->u.s.frac_width)); in divider()
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/linux/drivers/usb/common/
H A Dulpi.c1 // SPDX-License-Identifier: GPL-2.0
3 * ulpi.c - USB ULPI PHY bus
19 #include <linux/clk/clk-conf.h>
21 /* -------------------------------------------------------------------------- */
25 return ulpi->ops->read(ulpi->dev.parent, addr); in ulpi_read()
31 return ulpi->ops->write(ulpi->dev.parent, addr, val); in ulpi_write()
35 /* -------------------------------------------------------------------------- */
47 if (ulpi->id.vendor == 0 || !drv->id_table) in ulpi_match()
50 for (id = drv->id_table; id->vendor; id++) in ulpi_match()
51 if (id->vendor == ulpi->id.vendor && in ulpi_match()
[all …]
/linux/drivers/irqchip/
H A Dirq-al-fic.c1 // SPDX-License-Identifier: GPL-2.0
49 u32 control = readl_relaxed(fic->base + AL_FIC_CONTROL); in al_fic_set_trigger() local
53 control &= ~CONTROL_TRIGGER_RISING; in al_fic_set_trigger()
56 control |= CONTROL_TRIGGER_RISING; in al_fic_set_trigger()
58 gc->chip_types->handler = handler; in al_fic_set_trigger()
59 fic->state = new_state; in al_fic_set_trigger()
60 writel_relaxed(control, fic->base + AL_FIC_CONTROL); in al_fic_set_trigger()
66 struct al_fic *fic = gc->private; in al_fic_irq_set_type()
69 guard(raw_spinlock)(&gc->lock); in al_fic_irq_set_type()
74 return -EINVAL; in al_fic_irq_set_type()
[all …]
/linux/drivers/clk/
H A Dclk-gpio.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2013 - 2014 Texas Instruments Incorporated - https://www.ti.com
12 #include <linux/clk-provider.h>
26 * prepare - clk_(un)prepare are functional and control a gpio that can sleep
27 * enable - clk_enable and clk_disable are functional & control
28 * non-sleeping gpio
29 * rate - inherits rate from parent. No clk_set_rate support
30 * parent - fixed parent. No clk_set_parent support
34 * struct clk_gpio - gpio gated clock
36 * @hw: handle between common and hardware-specific interfaces
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/linux/Documentation/devicetree/bindings/remoteproc/
H A Dti,pru-rproc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,pru-rproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
13 Each Programmable Real-Time Unit and Industrial Communication Subsystem
14 (PRU-ICSS or PRUSS) has two 32-bit load/store RISC CPU cores called
15 Programmable Real-Time Units (PRUs), each represented by a node. Each PRU
16 core has a dedicated Instruction RAM, Control and Debug register sets, and
17 use the Data RAMs present within the PRU-ICSS for code execution.
[all …]
/linux/sound/aoa/soundbus/i2sbus/
H A Dcore.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright 2006-2008 Johannes Berg <johannes@sipsolutions.net>
12 #include <linux/dma-mapping.h>
32 " no layout-id property is present");
46 r->size = (numcmds + 3) * sizeof(struct dbdma_cmd); in alloc_dbdma_descriptor_ring()
48 * enough or until we get some macio-specific versions in alloc_dbdma_descriptor_ring()
50 r->spac in alloc_dbdma_descriptor_ring()
118 struct device_node *parent; i2sbus_get_and_fixup_rsrc() local
154 i2sbus_add_dev(struct macio_dev * macio,struct i2sbus_control * control,struct device_node * np) i2sbus_add_dev() argument
340 struct i2sbus_control *control = NULL; i2sbus_probe() local
370 struct i2sbus_control *control = dev_get_drvdata(&dev->ofdev.dev); i2sbus_remove() local
380 struct i2sbus_control *control = dev_get_drvdata(&dev->ofdev.dev); i2sbus_suspend() local
404 struct i2sbus_control *control = dev_get_drvdata(&dev->ofdev.dev); i2sbus_resume() local
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/linux/Documentation/devicetree/bindings/clock/ti/
H A Dti,mux-clock.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/ti/ti,mux-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tero Kristo <kristo@kernel.org>
13 This clock assumes a register-mapped multiplexer with multiple inpt clock
15 not gate or adjust the parent rate via a divider or multiplier.
24 register value selected parent clock
31 "index-starts-at-one" modified the scheme as follows:
33 register value selected clock parent
[all …]
/linux/fs/fuse/
H A Dcontrol.c3 Copyright (C) 2001-2008 Miklos Szeredi <miklos@szeredi.hu>
19 * This is non-NULL when the single instance of the control filesystem
28 fc = file_inode(file)->i_private; in fuse_ctl_file_conn_get()
40 if (fc->abort_err) in fuse_conn_abort_write()
41 fc->aborted = true; in fuse_conn_abort_write()
60 value = atomic_read(&fc->num_waiting); in fuse_conn_waiting_read()
61 file->private_data = (void *)value; in fuse_conn_waiting_read()
64 size = sprintf(tmp, "%ld\n", (long)file->private_data); in fuse_conn_waiting_read()
82 unsigned limit = (1 << 16) - 1; in fuse_conn_limit_write()
86 return -EINVAL; in fuse_conn_limit_write()
[all …]
/linux/arch/arm64/boot/dts/ti/
H A Dk3-am65-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/
7 #include <dt-bindings/phy/phy-am654-serdes.h>
11 compatible = "mmio-sram";
13 #address-cells = <1>;
14 #size-cells = <1>;
17 atf-sram@0 {
21 sysfw-sram@f0000 {
25 l3cache-sram@100000 {
30 gic500: interrupt-controller@1800000 {
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/linux/Documentation/devicetree/bindings/clock/
H A Dkeystone-pll.txt9 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
12 - #clock-cells : from common clock binding; shall be set to 0.
13 - compatible : shall be "ti,keystone,main-pll-clock" or "ti,keystone,pll-clock"
14 - clocks : parent clock phandle
15 - reg - pll control0 and pll multiplier registers
16 - reg-names : control, multiplier and post-divider. The multiplier and
17 post-divider registers are applicable only for main pll clock
18 - fixed-postdiv : fixed post divider value. If absent, use clkod register bits
23 #clock-cells = <0>;
24 compatible = "ti,keystone,main-pll-clock";
[all …]
/linux/drivers/gpio/
H A Dgpio-janz-ttl.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Janz MODULbus VMOD-TTL GPIO Driver
21 #define DRV_NAME "janz-ttl"
41 __be16 control; member
59 struct ttl_module *mod = dev_get_drvdata(gpio->parent); in ttl_get_value()
64 shadow = &mod->porta_shadow; in ttl_get_value()
66 shadow = &mod->portb_shadow; in ttl_get_value()
67 offset -= 8; in ttl_get_value()
69 shadow = &mod->portc_shadow; in ttl_get_value()
70 offset -= 16; in ttl_get_value()
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