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/linux/drivers/iio/multiplexer/
H A Diio-mux.c1 // SPDX-License-Identifier: GPL-2.0
32 struct mux_control *control; member
33 struct iio_channel *parent;
42 struct mux_child *child = &mux->child[idx]; in iio_mux_select()
43 struct iio_chan_spec const *chan = &mux->chan[idx]; in iio_mux_select()
47 ret = mux_control_select_delay(mux->control, chan->channe in iio_mux_select()
31 struct mux_control *control; global() member
331 struct iio_channel *parent; mux_probe() local
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/linux/Documentation/devicetree/bindings/mux/
H A Dreg-mux.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mux/reg-mux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic register bitfield-based multiplexer controller
10 - Peter Rosin <peda@axentia.se>
13 Define register bitfields to be used to control multiplexers. The parent
19 - reg-mux # parent device of mux controller is not syscon device
20 - mmio-mux # parent device of mux controller is syscon device
24 '#mux-control-cells':
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H A Dmux-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mux/mux-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Peter Rosin <peda@axentia.se>
14 that uses the mux controller. Thus, a mux controller can possibly control
17 control several multiplexers for a single consumer.
20 space is a simple zero-based enumeration. I.e. 0-1 for a 2-way multiplexer,
21 0-7 for an 8-way multiplexer, etc.
25 --------------------
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H A Dgpio-mux.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mux/gpio-mux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: GPIO-based multiplexer controller
10 - Peter Rosin <peda@axentia.se>
13 Define what GPIO pins are used to control a multiplexer. Or several
14 multiplexers, if the same pins control more than one multiplexer.
22 const: gpio-mux
24 mux-gpios:
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/linux/include/linux/firmware/imx/svc/
H A Dpm.h1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Copyright 2017-2018 NXP
8 * control, clock control, reset control, and wake-up event control.
56 #define IMX_SC_PM_PW_MODE_LP 2 /* Power in low-power */
77 * Defines for SC PM CLK Parent
79 #define IMX_SC_PM_PARENT_XTAL 0 /* Parent is XTAL. */
80 #define IMX_SC_PM_PARENT_PLL0 1 /* Parent is PLL0 */
81 #define IMX_SC_PM_PARENT_PLL1 2 /* Parent is PLL1 or PLL0/2 */
82 #define IMX_SC_PM_PARENT_PLL2 3 /* Parent in PLL2 or PLL0/4 */
83 #define IMX_SC_PM_PARENT_BYPS 4 /* Parent is a bypass clock. */
/linux/include/linux/
H A Dpowercap.h1 /* SPDX-License-Identifier: GPL-2.0-only */
24 * struct powercap_control_type_ops - Define control type callbacks
25 * @set_enable: Enable/Disable whole control type.
32 * control type is closed. So it is safe to free data
33 * structure associated with this control type.
35 * for the control type.
37 * This structure defines control type callbacks to be implemented by client
47 * struct powercap_control_type - Defines a powercap control_type
52 * @lock: mutex for control type
58 * @node: linked-list node
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/linux/drivers/acpi/acpica/
H A Dpsparse.c1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
4 * Module Name: psparse - Parser top level AML parse routines
6 * Copyright (C) 2000 - 2023, Intel Corp.
34 * PARAMETERS: opcode - An AML opcode
44 /* Extended (2-byte) opcode if > 255 */ in acpi_ps_get_opcode_size()
59 * PARAMETERS: parser_state - A parser state object
72 aml = parser_state->aml; in acpi_ps_peek_opcode()
90 * PARAMETERS: walk_state - Current State
91 * op - Op to complete
121 if (((walk_state->parse_flags & ACPI_PARSE_TREE_MASK) != in acpi_ps_complete_this_op()
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/linux/drivers/regulator/
H A Dtps65090-regulator.c1 // SPDX-License-Identifier: GPL-2.0-only
33 * struct tps65090_regulator - Per-regulator data for a tps65090 regulator
54 * tps65090_reg_set_overcurrent_wait - Setup overcurrent wait
62 * Return: 0 if no error, non-zero if there was an error writing the register.
69 ret = regmap_update_bits(rdev->regmap, rdev->desc->enable_reg, in tps65090_reg_set_overcurrent_wait()
71 ri->overcurrent_wait << CTRL_WT_BIT); in tps65090_reg_set_overcurrent_wait()
73 dev_err(&rdev->dev, "Error updating overcurrent wait %#x\n", in tps65090_reg_set_overcurrent_wait()
74 rdev->desc->enable_reg); in tps65090_reg_set_overcurrent_wait()
81 * tps65090_try_enable_fet - Try to enable a FET
85 * Return: 0 if ok, -ENOTRECOVERABLE if the FET power good bit did not get
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/linux/drivers/clk/bcm/
H A Dclk-kona-setup.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include "clk-kona.h"
13 #define selector_clear_exists(sel) ((sel)->width = 0)
20 struct ccu_policy *ccu_policy = &ccu->policy; in ccu_data_offsets_valid()
23 limit = ccu->range - sizeof(u32); in ccu_data_offsets_valid()
26 if (ccu_policy->enable.offset > limit) { in ccu_data_offsets_valid()
29 ccu->name, ccu_policy->enable.offset, limit); in ccu_data_offsets_valid()
32 if (ccu_policy->control.offset > limit) { in ccu_data_offsets_valid()
33 pr_err("%s: bad policy control offset for %s " in ccu_data_offsets_valid()
35 ccu->name, ccu_policy->control.offset, limit); in ccu_data_offsets_valid()
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H A Dclk-kona.h1 /* SPDX-License-Identifier: GPL-2.0-only */
16 #include <linux/clk-provider.h>
20 /* The common clock framework uses u8 to represent a parent index */
24 #define BAD_CLK_NAME ((const char *)-1)
33 #define FLAG_SET(obj, type, flag) ((obj)->flags |= FLAG(type, flag))
34 #define FLAG_CLEAR(obj, type, flag) ((obj)->flags &= ~(FLAG(type, flag)))
35 #define FLAG_FLIP(obj, type, flag) ((obj)->flags ^= FLAG(type, flag))
36 #define FLAG_TEST(obj, type, flag) (!!((obj)->flags & FLAG(type, flag)))
40 #define ccu_policy_exists(ccu_policy) ((ccu_policy)->enable.offset != 0)
44 #define policy_exists(policy) ((policy)->offset != 0)
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/linux/Documentation/devicetree/bindings/serial/
H A Dnxp,sc16is7xx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schema
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/linux/drivers/usb/common/
H A Dulpi.c1 // SPDX-License-Identifier: GPL-2.0
3 * ulpi.c - USB ULPI PHY bus
19 #include <linux/clk/clk-conf.h>
21 /* -------------------------------------------------------------------------- */
25 return ulpi->ops->read(ulpi->dev.parent, addr); in ulpi_read()
31 return ulpi->ops->write(ulpi->dev.parent, addr, val); in ulpi_write()
35 /* -------------------------------------------------------------------------- */
47 if (ulpi->id.vendor == 0 || !drv->id_table) in ulpi_match()
50 for (id = drv->id_table; id->vendor; id++) in ulpi_match()
51 if (id->vendor == ulpi->id.vendor && in ulpi_match()
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/linux/drivers/irqchip/
H A Dirq-al-fic.c1 // SPDX-License-Identifier: GPL-2.0
49 u32 control = readl_relaxed(fic->base + AL_FIC_CONTROL); in al_fic_set_trigger() local
53 control &= ~CONTROL_TRIGGER_RISING; in al_fic_set_trigger()
56 control |= CONTROL_TRIGGER_RISING; in al_fic_set_trigger()
58 gc->chip_types->handler = handler; in al_fic_set_trigger()
59 fic->state = new_state; in al_fic_set_trigger()
60 writel_relaxed(control, fic->base + AL_FIC_CONTROL); in al_fic_set_trigger()
66 struct al_fic *fic = gc->private; in al_fic_irq_set_type()
75 ret = -EINVAL; in al_fic_irq_set_type()
91 if (fic->state == AL_FIC_UNCONFIGURED) { in al_fic_irq_set_type()
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/linux/drivers/clk/
H A Dclk-gpio.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2013 - 2014 Texas Instruments Incorporated - https://www.ti.com
12 #include <linux/clk-provider.h>
26 * prepare - clk_(un)prepare are functional and control a gpio that can sleep
27 * enable - clk_enable and clk_disable are functional & control
28 * non-sleeping gpio
29 * rate - inherits rate from parent. No clk_set_rate support
30 * parent - fixed parent. No clk_set_parent support
34 * struct clk_gpio - gpio gated clock
36 * @hw: handle between common and hardware-specific interfaces
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/linux/drivers/hid/
H A Dhid-roccat-common.c1 // SPDX-License-Identifier: GPL-2.0-or-later
14 #include "hid-roccat-common.h"
29 return -ENOMEM; in roccat_common2_receive()
39 return ((len < 0) ? len : ((len != size) ? -EIO : 0)); in roccat_common2_receive()
51 return -ENOMEM; in roccat_common2_send()
60 return ((len < 0) ? len : ((len != size) ? -EIO : 0)); in roccat_common2_send()
75 struct roccat_common2_control control; in roccat_common2_receive_control_status() local
81 &control, sizeof(struct roccat_common2_control)); in roccat_common2_receive_control_status()
86 switch (control.value) { in roccat_common2_receive_control_status()
95 return -EINVAL; in roccat_common2_receive_control_status()
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/linux/Documentation/devicetree/bindings/remoteproc/
H A Dti,pru-rproc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,pru-rproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
13 Each Programmable Real-Time Unit and Industrial Communication Subsystem
14 (PRU-ICSS or PRUSS) has two 32-bit load/store RISC CPU cores called
15 Programmable Real-Time Units (PRUs), each represented by a node. Each PRU
16 core has a dedicated Instruction RAM, Control and Debug register sets, and
17 use the Data RAMs present within the PRU-ICSS for code execution.
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/linux/arch/arm64/boot/dts/ti/
H A Dk3-am65-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/
7 #include <dt-bindings/phy/phy-am654-serdes.h>
11 compatible = "mmio-sram";
13 #address-cells = <1>;
14 #size-cells = <1>;
17 atf-sram@0 {
21 sysfw-sram@f0000 {
25 l3cache-sram@100000 {
30 gic500: interrupt-controller@1800000 {
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/linux/drivers/gpio/
H A Dgpio-ixp4xx.c1 // SPDX-License-Identifier: GPL-2.0
6 // based on previous work and know-how from:
43 * Clock output control register defines.
55 * struct ixp4xx_gpio - IXP4 GPIO state container
58 * @base: remapped I/O-memory base
59 * @irq_edge: Each bit represents an IRQ: 1: edge-triggered,
74 __raw_writel(BIT(d->hwirq), g->base + IXP4XX_REG_GPIS); in ixp4xx_gpio_irq_ack()
82 gpiochip_disable_irq(gc, d->hwirq); in ixp4xx_gpio_mask_irq()
90 /* ACK when unmasking if not edge-triggered */ in ixp4xx_gpio_irq_unmask()
91 if (!(g->irq_edge & BIT(d->hwirq))) in ixp4xx_gpio_irq_unmask()
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/linux/include/media/
H A Dv4l2-ctrls.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
14 #include <media/media-request.h>
29 * union v4l2_ctrl_ptr - A pointer to a control value.
30 * @p_s32: Pointer to a 32-bit signed value.
31 * @p_s64: Pointer to a 64-bit signed value.
32 * @p_u8: Pointer to a 8-bit unsigned value.
33 * @p_u16: Pointer to a 16-bit unsigned value.
34 * @p_u32: Pointer to a 32-bit unsigned value.
97 * v4l2_ctrl_ptr_create() - Helper function to return a v4l2_ctrl_ptr from a
109 * struct v4l2_ctrl_ops - The control operations that the driver has to provide.
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/linux/sound/aoa/soundbus/i2sbus/
H A Dcore.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright 2006-2008 Johannes Berg <johannes@sipsolutions.net>
12 #include <linux/dma-mapping.h>
32 " no layout-id property is present");
46 r->size = (numcmds + 3) * sizeof(struct dbdma_cmd); in alloc_dbdma_descriptor_ring()
48 * enough or until we get some macio-specific versions in alloc_dbdma_descriptor_ring()
50 r->space = dma_alloc_coherent(&macio_get_pci_dev(i2sdev->macio)->dev, in alloc_dbdma_descriptor_ring()
51 r->size, &r->bus_addr, GFP_KERNEL); in alloc_dbdma_descriptor_ring()
52 if (!r->space) in alloc_dbdma_descriptor_ring()
53 return -ENOMEM; in alloc_dbdma_descriptor_ring()
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/linux/Documentation/devicetree/bindings/clock/ti/
H A Dti,mux-clock.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/ti/ti,mux-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tero Kristo <kristo@kernel.org>
13 This clock assumes a register-mapped multiplexer with multiple inpt clock
15 not gate or adjust the parent rate via a divider or multiplier.
24 register value selected parent clock
31 "index-starts-at-one" modified the scheme as follows:
33 register value selected clock parent
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/linux/drivers/clk/ingenic/
H A Dcgu.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * Copyright (c) 2013-2015 Imagination Technologies
13 #include <linux/clk-provider.h>
18 * struct ingenic_cgu_pll_info - information about a PLL
19 * @reg: the offset of the PLL's control register within the CGU
23 * control register)
25 * @m_offset: the multiplier value which encodes to 0 in the PLL's control
29 * control register)
31 * @n_offset: the divider value which encodes to 0 in the PLL's control
33 * @od_shift: the number of bits to shift the post-VCO divider value by (ie.
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/linux/drivers/net/mdio/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
20 loadable module or built-in.
58 tristate "APM X-Gene SoC MDIO bus controller"
62 APM X-Gene SoC's.
72 third revision of the ASPEED MDIO register interface - the first two
109 tristate "GPIO lib-based bitbanged MDIO buses"
113 Supports GPIO lib-based MDIO busses.
116 will be called mdio-gpio.
177 IPQ40xx, IPQ60xx, IPQ807x and IPQ50xx series Soc-s.
193 layout. It's regmap-based so that it can be used on integrated,
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/linux/fs/fuse/
H A Dcontrol.c3 Copyright (C) 2001-2008 Miklos Szeredi <miklos@szeredi.hu>
18 * This is non-NULL when the single instance of the control filesystem
27 fc = file_inode(file)->i_private; in fuse_ctl_file_conn_get()
39 if (fc->abort_err) in fuse_conn_abort_write()
40 fc->aborted = true; in fuse_conn_abort_write()
59 value = atomic_read(&fc->num_waiting); in fuse_conn_waiting_read()
60 file->private_data = (void *)value; in fuse_conn_waiting_read()
63 size = sprintf(tmp, "%ld\n", (long)file->private_data); in fuse_conn_waiting_read()
81 unsigned limit = (1 << 16) - 1; in fuse_conn_limit_write()
85 return -EINVAL; in fuse_conn_limit_write()
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/linux/drivers/hwtracing/coresight/
H A Dcoresight-tpdm.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/coresight-pmu.h>
19 #include "coresight-priv.h"
20 #include "coresight-tpdm.h"
29 struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); in tpdm_simple_dataset_show()
33 switch (tpdm_attr->mem) { in tpdm_simple_dataset_show()
35 if (tpdm_attr->id in tpdm_simple_dataset_show()
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