continuous\-burst\-clk (full) in projects: linux

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Searched +full:continuous +full:- +full:burst +full:- +full:clk (Results 1 – 10 of 10) sorted by relevance

/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/fsl/
H A D	fsl,imx-weim.yaml	`1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/memory-controllers/fsl/fsl,imx-weim.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Shawn Guo <shawnguo@kernel.org> 11 - Sascha Hauer <s.hauer@pengutronix.de> 16 wireless and mobile applications that use low-power technology. The actual 21 pattern: "^memory-controller@[0-9a-f]+$" 25 - enum: 26 - fsl,imx1-weim [all …]`
/freebsd/sys/contrib/device-tree/Bindings/bus/
H A D	imx-weim.txt	`5 wireless and mobile applications that use low-power technology. 11 - compatible: Should contain one of the following: 12 "fsl,imx1-weim" 13 "fsl,imx27-weim" 14 "fsl,imx51-weim" 15 "fsl,imx50-weim" 16 "fsl,imx6q-weim" 17 - reg: A resource specifier for the register space 19 - clocks: the clock, see the example below. 20 - #address-cells: Must be set to 2 to allow memory address translation [all …]`
/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/
H A D	st,stm32-fmc2-ebi-props.yaml	`1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/memory-controllers/st,stm32-fmc2-ebi-props.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Christophe Kerello <christophe.kerello@foss.st.com> 11 - Marek Vasut <marex@denx.de> 14 st,fmc2-ebi-cs-transaction-type: 33 st,fmc2-ebi-cs-cclk-enable: 34 description: Continuous clock enable (first bank must be configured 40 st,fmc2-ebi-cs-mux-enable: [all …]`
/freebsd/sys/dev/ath/ath_hal/ar5210/
H A D	ar5210reg.h	1 /- 2 SPDX-License-Identifier: ISC 4 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 5 * Copyright (c) 2002-2004 Atheros Communications, Inc. 24 * Processor for IEEE 802.11a 5-GHz Wireless LANs. 72 #define AR_SLOT_TIME 0x8010 /* Length of a back-off / 98 #define AR_BACKOFF 0x8088 / Back-off status / 127 #define AR_CFG_TXFSTRT 0x00010000 / re-enable TX DMA / 184 #define AR_IER_DISABLE 0x00000000 / pseudo-flag / 190 #define AR_BCR_TQ1FV 0x00000004 / use TXQ1 for non-beacon */ [all …]
/illumos-gate/usr/src/uts/common/io/qede/579xx/hsi/hw/
H A D	reg_addr_ah_compile15.h	9 * or http://opensource.org/licenses/CDDL-1.0. 23 * Copyright 2014-2017 Cavium, Inc. 30 * at http://opensource.org/licenses/CDDL-1.0 85 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of … 87 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… 96 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… 98 … has_mem_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… 144 …_SYS_ERR (0x1<<30) // Fatal or Non-Fatal Error Message s… 148 …:0x20 This is the PCIE compliant status/command register (bits 31-16: status, bits 15-0: command)… 149 …:0x20 This is the PCIE compliant status/command register (bits 31-16: status, bits 15-0: command)… [all …]
H A D	reg_addr_bb.h	9 * or http://opensource.org/licenses/CDDL-1.0. 23 * Copyright 2014-2017 Cavium, Inc. 30 * at http://opensource.org/licenses/CDDL-1.0 84 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl… 85 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea… 86 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn… 87 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea… 89 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of … 91 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… 99 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… [all …]
H A D	reg_addr_k2.h	9 * or http://opensource.org/licenses/CDDL-1.0. 23 * Copyright 2014-2017 Cavium, Inc. 30 * at http://opensource.org/licenses/CDDL-1.0 84 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl… 85 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea… 86 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn… 87 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea… 89 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of … 91 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… 99 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… [all …]
H A D	reg_addr_e5.h	9 * or http://opensource.org/licenses/CDDL-1.0. 23 * Copyright 2014-2017 Cavium, Inc. 30 * at http://opensource.org/licenses/CDDL-1.0 84 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl… 85 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea… 86 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn… 87 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea… 89 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of … 91 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… 99 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… [all …]
H A D	reg_addr.h	9 * or http://opensource.org/licenses/CDDL-1.0. 23 * Copyright 2014-2017 Cavium, Inc. 30 * at http://opensource.org/licenses/CDDL-1.0 85 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl… 86 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea… 87 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn… 88 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea… 90 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of … 92 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… 100 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… [all …]
/freebsd/sys/dev/qlnx/qlnxe/
H A D	reg_addr.h	2 * Copyright (c) 2017-2018 Cavium, Inc. 78 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl… 79 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea… 80 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn… 81 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea… 88 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of … 90 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… 116 … (0x1<<9) // Fast back-to-back transaction ena… 128 … (0x1<<23) // Fast back-to-back capable. Not ap… 145 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… [all …]