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/linux/drivers/perf/amlogic/
H A Dmeson_g12_ddr_pmu.c44 PMU_FORMAT_ATTR(arm, "config1:0");
45 PMU_FORMAT_ATTR(gpu, "config1:1");
46 PMU_FORMAT_ATTR(pcie, "config1:2");
47 PMU_FORMAT_ATTR(hdcp, "config1:3");
48 PMU_FORMAT_ATTR(hevc_front, "config1:4");
49 PMU_FORMAT_ATTR(usb3_0, "config1:6");
50 PMU_FORMAT_ATTR(device, "config1:7");
51 PMU_FORMAT_ATTR(hevc_back, "config1:8");
52 PMU_FORMAT_ATTR(h265enc, "config1:9");
53 PMU_FORMAT_ATTR(vpu_read1, "config1:16");
[all …]
H A Dmeson_ddr_pmu_core.c121 u64 config1 = event->attr.config1; in meson_ddr_perf_event_init() local
135 hweight64(config1) + hweight64(config2) > MAX_AXI_PORTS_OF_CHANNEL) in meson_ddr_perf_event_init()
153 u64 config1 = event->attr.config1; in meson_ddr_perf_event_add() local
158 (const unsigned long *)&config1, in meson_ddr_perf_event_add()
159 BITS_PER_TYPE(config1)) in meson_ddr_perf_event_add()
299 char value[20]; // config1:xxx, 20 is enough in meson_ddr_perf_format_attr_visible()
304 if (sscanf(value, "config1:%d", &id) == 1) in meson_ddr_perf_format_attr_visible()
/linux/Documentation/ABI/testing/
H A Dsysfs-bus-event_source-devices-iommu7 perf_event_attr.config1 or perf_event_attr.config2 for
12 perf_event_attr.config, perf_event_attr.config1,
20 filter_requester_en = "config1:0" - Enable Requester ID filter
21 filter_domain_en = "config1:1" - Enable Domain ID filter
22 filter_pasid_en = "config1:2" - Enable PASID filter
23 filter_ats_en = "config1:3" - Enable Address Type filter
24 filter_page_table_en= "config1:4" - Enable Page Table Level filter
25 filter_requester_id = "config1:16-31" - Requester ID filter
26 filter_domain = "config1:32-47" - Domain ID filter
H A Dsysfs-bus-event_source-devices-dsa7 perf_event_attr.config1 for the IDXD DSA pmu. (See also
11 perf_event_attr.config or perf_event_attr.config1.
18 filter_wq = "config1:0-31" - workqueue filter
19 filter_tc = "config1:32-39" - traffic class filter
20 filter_pgsz = "config1:40-43" - page size filter
21 filter_sz = "config1:44-51" - transfer size filter
22 filter_eng = "config1:52-59" - engine filter
/linux/drivers/phy/socionext/
H A Dphy-uniphier-usb2.c36 struct uniphier_u2phy_param config1; member
77 regmap_write(priv->regmap, priv->data->config1.offset, in uniphier_u2phy_init()
78 priv->data->config1.value); in uniphier_u2phy_init()
187 .config1 = { SG_USBPHY12PLL, 0x00010010 },
191 .config1 = { SG_USBPHY12PLL, 0x00010010 },
195 .config1 = { SG_USBPHY34PLL, 0x00010010 },
199 .config1 = { SG_USBPHY34PLL, 0x00010010 },
207 .config1 = { SG_USBPHY1CTRL2, 0x00000106 },
211 .config1 = { SG_USBPHY2CTRL2, 0x00000106 },
215 .config1 = { SG_USBPHY3CTRL2, 0x00000106 },
H A Dphy-uniphier-usb3hs.c82 u32 config1; member
255 u32 config0, config1; in uniphier_u3hsphy_init() local
275 || (!priv->data->config0 && !priv->data->config1)) in uniphier_u3hsphy_init()
279 config1 = priv->data->config1; in uniphier_u3hsphy_init()
286 writel(config1, priv->base + HSPHY_CFG1); in uniphier_u3hsphy_init()
418 .config1 = 0x00000106,
430 .config1 = 0x00000106,
/linux/arch/powerpc/platforms/83xx/
H A Dsuspend.c62 u32 config1; member
123 u32 reg_cfg1 = in_be32(&pmc_regs->config1); in mpc83xx_change_state()
133 out_be32(&pmc_regs->config1, reg_cfg1); in mpc83xx_change_state()
185 out_be32(&pmc_regs->config1, in mpc83xx_suspend_enter()
186 in_be32(&pmc_regs->config1) | PMCCR1_PME_EN); in mpc83xx_suspend_enter()
206 out_be32(&pmc_regs->config1, in mpc83xx_suspend_enter()
207 in_be32(&pmc_regs->config1) | PMCCR1_POWER_OFF); in mpc83xx_suspend_enter()
214 out_be32(&pmc_regs->config1, in mpc83xx_suspend_enter()
215 in_be32(&pmc_regs->config1) & ~PMCCR1_POWER_OFF); in mpc83xx_suspend_enter()
229 out_be32(&pmc_regs->config1, in mpc83xx_suspend_enter()
[all …]
/linux/tools/testing/selftests/powerpc/pmu/event_code_tests/
H A Dgroup_constraint_thresh_cmp_test.c43 /* Add the thresh_cmp value for leader in config1 */ in group_constraint_thresh_cmp()
44 leader.attr.config1 = 1000; in group_constraint_thresh_cmp()
49 /* Add the different thresh_cmp value from the leader event in config1 */ in group_constraint_thresh_cmp()
50 event.attr.config1 = 2000; in group_constraint_thresh_cmp()
60 /* Add the same thresh_cmp value for leader and sibling event in config1 */ in group_constraint_thresh_cmp()
61 event.attr.config1 = 1000; in group_constraint_thresh_cmp()
/linux/drivers/staging/iio/addac/
H A Dadt7316.c89 * ADT7316 config1
184 u8 config1; member
219 return sprintf(buf, "%d\n", !!(chip->config1 & ADT7316_EN)); in adt7316_show_enabled()
225 u8 config1; in _adt7316_store_enabled() local
229 config1 = chip->config1 | ADT7316_EN; in _adt7316_store_enabled()
231 config1 = chip->config1 & ~ADT7316_EN; in _adt7316_store_enabled()
233 ret = chip->bus.write(chip->bus.client, ADT7316_CONFIG1, config1); in _adt7316_store_enabled()
237 chip->config1 = config1; in _adt7316_store_enabled()
277 return sprintf(buf, "%d\n", !!(chip->config1 & ADT7516_SEL_EX_TEMP)); in adt7316_show_select_ex_temp()
287 u8 config1; in adt7316_store_select_ex_temp() local
[all …]
/linux/drivers/hwmon/
H A Dlm90.c1799 static const char *lm90_detect_max1617(struct i2c_client *client, int config1) in lm90_detect_max1617() argument
1807 if (config1 & 0x3f) in lm90_detect_max1617()
1859 (config1 | 0xff00)) in lm90_detect_max1617()
1870 int config1, int convrate) in lm90_detect_national() argument
1879 if ((config1 & 0x2a) || (config2 & 0xf8) || convrate > 0x09) in lm90_detect_national()
1904 static const char *lm90_detect_on(struct i2c_client *client, int chip_id, int config1, in lm90_detect_on() argument
1912 if ((address == 0x4c || address == 0x4d) && !(config1 & 0x1b) && in lm90_detect_on()
1923 int chip_id, int config1, int convrate) in lm90_detect_analog() argument
1975 !(status & 0x03) && !(config1 & 0x3f) && !(convrate & 0xf8)) in lm90_detect_analog()
1981 (config1 & 0x0b) == 0x08 && convrate <= 0x0a) in lm90_detect_analog()
[all …]
/linux/drivers/perf/hisilicon/
H A Dhisi_uncore_sllc_pmu.c45 HISI_PMU_EVENT_ATTR_EXTRACTOR(tgtid_min, config1, 10, 0);
46 HISI_PMU_EVENT_ATTR_EXTRACTOR(tgtid_max, config1, 21, 11);
47 HISI_PMU_EVENT_ATTR_EXTRACTOR(srcid_cmd, config1, 32, 22);
48 HISI_PMU_EVENT_ATTR_EXTRACTOR(srcid_msk, config1, 43, 33);
49 HISI_PMU_EVENT_ATTR_EXTRACTOR(tracetag_en, config1, 44, 44);
154 if (event->attr.config1 != 0x0) { in hisi_sllc_pmu_enable_filter()
163 if (event->attr.config1 != 0x0) { in hisi_sllc_pmu_clear_filter()
323 HISI_PMU_FORMAT_ATTR(tgtid_min, "config1:0-10"),
324 HISI_PMU_FORMAT_ATTR(tgtid_max, "config1:11-21"),
325 HISI_PMU_FORMAT_ATTR(srcid_cmd, "config1:22-32"),
[all …]
H A Dhisi_uncore_pa_pmu.c49 HISI_PMU_EVENT_ATTR_EXTRACTOR(tgtid_cmd, config1, 10, 0);
50 HISI_PMU_EVENT_ATTR_EXTRACTOR(tgtid_msk, config1, 21, 11);
51 HISI_PMU_EVENT_ATTR_EXTRACTOR(srcid_cmd, config1, 32, 22);
52 HISI_PMU_EVENT_ATTR_EXTRACTOR(srcid_msk, config1, 43, 33);
53 HISI_PMU_EVENT_ATTR_EXTRACTOR(tracetag_en, config1, 44, 44);
135 if (event->attr.config1 != 0x0) { in hisi_pa_pmu_enable_filter()
144 if (event->attr.config1 != 0x0) { in hisi_pa_pmu_disable_filter()
308 HISI_PMU_FORMAT_ATTR(tgtid_cmd, "config1:0-10"),
309 HISI_PMU_FORMAT_ATTR(tgtid_msk, "config1:11-21"),
310 HISI_PMU_FORMAT_ATTR(srcid_cmd, "config1:22-32"),
[all …]
H A Dhisi_uncore_hha_pmu.c54 HISI_PMU_EVENT_ATTR_EXTRACTOR(srcid_cmd, config1, 10, 0);
55 HISI_PMU_EVENT_ATTR_EXTRACTOR(srcid_msk, config1, 21, 11);
56 HISI_PMU_EVENT_ATTR_EXTRACTOR(tracetag_en, config1, 22, 22);
57 HISI_PMU_EVENT_ATTR_EXTRACTOR(datasrc_skt, config1, 23, 23);
143 if (event->attr.config1 != 0x0) { in hisi_hha_pmu_enable_filter()
152 if (event->attr.config1 != 0x0) { in hisi_hha_pmu_disable_filter()
349 HISI_PMU_FORMAT_ATTR(srcid_cmd, "config1:0-10"),
350 HISI_PMU_FORMAT_ATTR(srcid_msk, "config1:11-21"),
351 HISI_PMU_FORMAT_ATTR(tracetag_en, "config1:22"),
352 HISI_PMU_FORMAT_ATTR(datasrc_skt, "config1:23"),
H A Dhisi_uncore_l3c_pmu.c58 HISI_PMU_EVENT_ATTR_EXTRACTOR(tt_core, config1, 7, 0);
59 HISI_PMU_EVENT_ATTR_EXTRACTOR(tt_req, config1, 10, 8);
60 HISI_PMU_EVENT_ATTR_EXTRACTOR(datasrc_cfg, config1, 15, 11);
61 HISI_PMU_EVENT_ATTR_EXTRACTOR(datasrc_skt, config1, 16, 16);
209 if (event->attr.config1 != 0x0) { in hisi_l3c_pmu_enable_filter()
218 if (event->attr.config1 != 0x0) { in hisi_l3c_pmu_disable_filter()
397 HISI_PMU_FORMAT_ATTR(tt_core, "config1:0-7"),
398 HISI_PMU_FORMAT_ATTR(tt_req, "config1:8-10"),
399 HISI_PMU_FORMAT_ATTR(datasrc_cfg, "config1:11-15"),
400 HISI_PMU_FORMAT_ATTR(datasrc_skt, "config1:16"),
H A Dhisi_uncore_uc_pmu.c49 HISI_PMU_EVENT_ATTR_EXTRACTOR(rd_req_en, config1, 0, 0);
50 HISI_PMU_EVENT_ATTR_EXTRACTOR(uring_channel, config1, 5, 4);
51 HISI_PMU_EVENT_ATTR_EXTRACTOR(srcid, config1, 19, 6);
52 HISI_PMU_EVENT_ATTR_EXTRACTOR(srcid_en, config1, 20, 20);
211 if (event->attr.config1 == 0) in hisi_uc_pmu_enable_filter()
221 if (event->attr.config1 == 0) in hisi_uc_pmu_disable_filter()
405 HISI_PMU_FORMAT_ATTR(rd_req_en, "config1:0-0"),
406 HISI_PMU_FORMAT_ATTR(uring_channel, "config1:4-5"),
407 HISI_PMU_FORMAT_ATTR(srcid, "config1:6-19"),
408 HISI_PMU_FORMAT_ATTR(srcid_en, "config1:20-20"),
/linux/arch/x86/events/intel/
H A Duncore_nhmex.c198 DEFINE_UNCORE_FORMAT_ATTR(match, match, "config1:0-63");
373 reg1->config = event->attr.config1; in nhmex_bbox_hw_config()
458 reg1->config = event->attr.config1; in nhmex_sbox_hw_config()
675 u64 config1 = reg1->config; in nhmex_mbox_get_constraint() local
688 __BITS_VALUE(config1, i, 32))) in nhmex_mbox_get_constraint()
727 config1 = nhmex_mbox_alter_er(event, idx[0], false); in nhmex_mbox_get_constraint()
777 * config1 to pass two MSRs' config. in nhmex_mbox_hw_config()
782 if (event->attr.config1 & ~er->valid_mask) in nhmex_mbox_hw_config()
799 reg1->config = event->attr.config1; in nhmex_mbox_hw_config()
875 DEFINE_UNCORE_FORMAT_ATTR(dsp, dsp, "config1:0-31");
[all …]
/linux/Documentation/admin-guide/perf/
H A Dxgene-pmu.rst19 config1 (agent ID) fields of the perf_event_attr structure. The "events"
30 to a corresponding bit in "config1" field. By default, the event will be
31 counted for all agent requests (config1 = 0x0). For all the supported agents of
46 / # perf stat -a -e l3c0/read-miss,config1=0xfffffffffffffffe/ sleep 1
/linux/drivers/iommu/intel/
H A Dperfmon.c77 IOMMU_PMU_ATTR(filter_requester_id_en, "config1:0", IOMMU_PMU_FILTER_REQUESTER_ID);
78 IOMMU_PMU_ATTR(filter_domain_en, "config1:1", IOMMU_PMU_FILTER_DOMAIN);
79 IOMMU_PMU_ATTR(filter_pasid_en, "config1:2", IOMMU_PMU_FILTER_PASID);
80 IOMMU_PMU_ATTR(filter_ats_en, "config1:3", IOMMU_PMU_FILTER_ATS);
81 IOMMU_PMU_ATTR(filter_page_table_en, "config1:4", IOMMU_PMU_FILTER_PAGE_TABLE);
82 IOMMU_PMU_ATTR(filter_requester_id, "config1:16-31", IOMMU_PMU_FILTER_REQUESTER_ID);
83 IOMMU_PMU_ATTR(filter_domain, "config1:32-47", IOMMU_PMU_FILTER_DOMAIN);
416 iommu_pmu_set_filter(requester_id, event->attr.config1, in iommu_pmu_assign_event()
418 event->attr.config1); in iommu_pmu_assign_event()
419 iommu_pmu_set_filter(domain, event->attr.config1, in iommu_pmu_assign_event()
[all …]
/linux/drivers/perf/arm_cspmu/
H A Dampere_cspmu.c36 SOC_PMU_EVENT_ATTR_EXTRACTOR(threshold, config1, 0, 7);
37 SOC_PMU_EVENT_ATTR_EXTRACTOR(rank, config1, 8, 23);
38 SOC_PMU_EVENT_ATTR_EXTRACTOR(bank, config1, 24, 55);
105 ARM_CSPMU_FORMAT_ATTR(threshold, "config1:0-7"),
106 ARM_CSPMU_FORMAT_ATTR(rank, "config1:8-23"),
107 ARM_CSPMU_FORMAT_ATTR(bank, "config1:24-55"),
/linux/drivers/gpu/drm/vc4/
H A Dvc4_vec.c244 u32 config1; member
280 .config1 = VEC_CONFIG1_C_CVBS_CVBS,
286 .config1 = VEC_CONFIG1_C_CVBS_CVBS | VEC_CONFIG1_CUSTOM_FREQ,
293 .config1 = VEC_CONFIG1_C_CVBS_CVBS,
299 .config1 = VEC_CONFIG1_C_CVBS_CVBS,
306 .config1 = VEC_CONFIG1_C_CVBS_CVBS | VEC_CONFIG1_CUSTOM_FREQ,
313 .config1 = VEC_CONFIG1_C_CVBS_CVBS,
319 .config1 = VEC_CONFIG1_C_CVBS_CVBS,
325 .config1 = VEC_CONFIG1_C_CVBS_CVBS,
334 .config1 = VEC_CONFIG1_C_CVBS_CVBS,
[all …]
/linux/drivers/net/ethernet/seeq/
H A Dether3.c119 ether3_outw(priv(dev)->regs.config1 | CFG1_LOCBUFMEM, REG_CONFIG1); in ether3_setbuffer()
273 priv(dev)->regs.config1 = CFG1_RECVCOMPSTAT0|CFG1_DMABURST8; in ether3_init_2()
280 ether3_outw(priv(dev)->regs.config1 | CFG1_BUFSELSTAT0, REG_CONFIG1); in ether3_init_2()
285 priv(dev)->regs.config1 |= CFG1_RECVPROMISC; in ether3_init_2()
287 priv(dev)->regs.config1 |= CFG1_RECVSPECBRMULTI; in ether3_init_2()
289 priv(dev)->regs.config1 |= CFG1_RECVSPECBROAD; in ether3_init_2()
296 ether3_outw(priv(dev)->regs.config1 | CFG1_TRANSEND, REG_CONFIG1); in ether3_init_2()
302 ether3_outw(priv(dev)->regs.config1 | CFG1_LOCBUFMEM, REG_CONFIG1); in ether3_init_2()
331 ether3_outw(priv(dev)->regs.config1 | CFG1_BUFSELSTAT0, REG_CONFIG1); in ether3_init_for_open()
340 ether3_outw(priv(dev)->regs.config1 | CFG1_TRANSEND, REG_CONFIG1); in ether3_init_for_open()
[all …]
/linux/drivers/mtd/nand/raw/
H A Dmxc_nand.c146 * (CONFIG1:INT_MSK is set). To handle this the driver uses
147 * enable_irq/disable_irq_nosync instead of CONFIG1:INT_MSK
674 uint16_t config1; in mxc_nand_enable_hwecc_v1_v2() local
679 config1 = readw(NFC_V1_V2_CONFIG1); in mxc_nand_enable_hwecc_v1_v2()
682 config1 |= NFC_V1_V2_CONFIG1_ECC_EN; in mxc_nand_enable_hwecc_v1_v2()
684 config1 &= ~NFC_V1_V2_CONFIG1_ECC_EN; in mxc_nand_enable_hwecc_v1_v2()
686 writew(config1, NFC_V1_V2_CONFIG1); in mxc_nand_enable_hwecc_v1_v2()
1001 uint16_t config1 = 0; in preset_v1() local
1005 config1 |= NFC_V1_V2_CONFIG1_ECC_EN; in preset_v1()
1008 config1 |= NFC_V1_V2_CONFIG1_INT_MSK; in preset_v1()
[all …]
/linux/arch/mips/mm/
H A Dc-octeon.c174 unsigned int config1; in probe_octeon() local
178 config1 = read_c0_config1(); in probe_octeon()
182 c->icache.linesz = 2 << ((config1 >> 19) & 7); in probe_octeon()
183 c->icache.sets = 64 << ((config1 >> 22) & 7); in probe_octeon()
184 c->icache.ways = 1 + ((config1 >> 16) & 7); in probe_octeon()
202 c->icache.linesz = 2 << ((config1 >> 19) & 7); in probe_octeon()
/linux/arch/mips/cavium-octeon/executive/
H A Dcvmx-pko.c297 union cvmx_pko_reg_queue_ptrs1 config1; in cvmx_pko_shutdown() local
298 config1.u64 = 0; in cvmx_pko_shutdown()
299 config1.s.qid7 = queue >> 7; in cvmx_pko_shutdown()
300 cvmx_write_csr(CVMX_PKO_REG_QUEUE_PTRS1, config1.u64); in cvmx_pko_shutdown()
333 union cvmx_pko_reg_queue_ptrs1 config1; in cvmx_pko_config_port() local
425 config1.u64 = 0; in cvmx_pko_config_port()
426 config1.s.idx3 = queue >> 3; in cvmx_pko_config_port()
427 config1.s.qid7 = (base_queue + queue) >> 7; in cvmx_pko_config_port()
529 cvmx_write_csr(CVMX_PKO_REG_QUEUE_PTRS1, config1.u64); in cvmx_pko_config_port()
/linux/tools/perf/tests/
H A Dpmu.c55 { "krava11", "config1:0,2,4,6,8,20-28\n", }, in test_pmu_get()
56 { "krava12", "config1:63\n", }, in test_pmu_get()
57 { "krava13", "config1:45-47\n", }, in test_pmu_get()
189 if (attr.config1 != 0x8000400000000145) { in test__pmu_format()
190 pr_err("Unexpected config1 value %llx\n", attr.config1); in test__pmu_format()
240 if (attr->config1 != 0x8000400000000145) { in test__pmu_events()
241 pr_err("Unexpected config1 value %llx\n", attr->config1); in test__pmu_events()

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