Searched full:coherently (Results 1 – 8 of 8) sorted by relevance
19 OpenCAPI allows FPGA and ASIC accelerators to be coherently
23 @ We probe for the active serial port here, coherently with
36 * disabled coherently. E.g. a CPU can technically enumerate supported for
56 /* Mask of CPUs which are currently definitely operating coherently */
323 * memory coherently. We default to pgprot_noncached which is usually used
633 * In the legacy case, ensure our coherently-allocated virtio in virtio_mmio_probe()
1132 * used coherently by the cores and GIC. Our only option is to mark in gicv5_its_init_bases()
1248 * enabled to make sure hardware sees them coherently. in msc_buffer_relink()