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/linux/tools/memory-model/Documentation/
H A Dglossary.txt42 Coherence (co): When one CPU's store to a given variable overwrites
44 there is said to be a coherence link from the second CPU to
47 It is also possible to have a coherence link within a CPU, which
48 is a "coherence internal" (coi) link. The term "coherence
115 See also "Coherence" and "Reads-from".
149 coherence and from-reads links.
156 See also Coherence" and "From-reads".
H A Dexplanation.txt19 11. CACHE COHERENCE AND THE COHERENCE ORDER RELATION: co, coi, and coe
608 CACHE COHERENCE AND THE COHERENCE ORDER RELATION: co, coi, and coe
611 Cache coherence is a general principle requiring that in a
615 ordering which all the CPUs agree on (the coherence order), and this
619 To put it another way, for any variable x, the coherence order (co) of
622 comes first in the coherence order; the store which directly
626 You can think of the coherence order as being the order in which the
630 coherence order, that is, if the value stored by W gets overwritten,
633 Coherence order is required to be consistent with program order. This
636 Write-write coherence: If W ->po-loc W' (i.e., W comes before
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/linux/Documentation/ABI/testing/
H A Dsysfs-firmware-sgi_uv35 The coherence_id entry contains the coherence id.
36 A partitioned UV system can have one or more coherence
37 domains. The coherence id indicates which coherence domain
/linux/tools/memory-model/litmus-tests/
H A DREADME6 Test of read-read coherence, that is, whether or not two
10 Test of read-write coherence, that is, whether or not a read
15 Test of write-read coherence, that is, whether or not a write
20 Test of write-write coherence, that is, whether or not two
H A DCoWW+poonceonce.litmus6 * Test of write-write coherence, that is, whether or not two successive
H A DCoRR+poonceonce+Once.litmus6 * Test of read-read coherence, that is, whether or not two successive
H A DCoRW+poonceonce+Once.litmus6 * Test of read-write coherence, that is, whether or not a read from
H A DCoWR+poonceonce+Once.litmus6 * Test of write-read coherence, that is, whether or not a write to a
H A DZ6.0+pooncerelease+poacquirerelease+fencembonceonce.litmus10 * is a write-to-write link (AKA a "coherence" or just "co" link) and P2()
/linux/tools/memory-model/
H A Dlinux-kernel.cat75 (* Fundamental coherence ordering *)
80 acyclic po-loc | com as coherence
214 (* Coherence requirements for plain accesses *)
218 empty (wr-incoh | rw-incoh | ww-incoh) as plain-coherence
H A DREADME183 satisfy the model's "coherence", "atomic", "happens-before",
217 for generation of the possible reads-from and coherence order
/linux/arch/arm/mach-mvebu/
H A Dcoherency.c72 * The "Shared L2 Present" bit affects the "level of coherence" value
75 * that included in the defined level of coherence. When HW I/O
/linux/arch/mips/include/asm/
H A Dmips-cps.h162 * zero if no Coherence Manager is present.
179 * if no Coherence Manager is present.
H A Dpm-cps.h11 * The CM & CPC can only handle coherence & power control on a per-core basis,
/linux/Documentation/devicetree/bindings/perf/
H A Dmarvell-cn10k-tad.yaml13 The Tag-and-Data units (TADs) maintain coherence and contain CN10K
/linux/arch/powerpc/boot/dts/fsl/
H A De500v1_power_isa.dtsi45 power-isa-mmc; // Memory Coherence
H A De500v2_power_isa.dtsi45 power-isa-mmc; // Memory Coherence
H A De500mc_power_isa.dtsi53 power-isa-mmc; // Memory Coherence
H A De5500_power_isa.dtsi53 power-isa-mmc; // Memory Coherence
H A De6500_power_isa.dtsi53 power-isa-mmc; // Memory Coherence
/linux/drivers/crypto/ccree/
H A Dcc_aead.h66 /* used to prevent cache coherence problem */
/linux/arch/arm64/kernel/
H A Dhibernate-asm.S35 * text to the Point of Coherence (PoC) before secondary cores can be booted.
/linux/arch/powerpc/include/asm/nohash/
H A Dpte-e500.h32 #define _PAGE_COHERENT 0x200000 /* M: enforce memory coherence */
/linux/drivers/iommu/
H A Dfsl_pamu.c582 * Create a coherence subdomain for a given memory block.
654 /* Find an unused coherence subdomain ID */ in create_csd()
855 /* Determine the Port ID for our coherence subdomain */ in fsl_pamu_probe()
871 dev_err(dev, "could not create coherence subdomain\n"); in fsl_pamu_probe()
/linux/drivers/net/ethernet/freescale/fman/
H A Dfman_port.h19 * coherence and returns error if applicable.

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