Searched full:coherence (Results 1 – 25 of 36) sorted by relevance
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/freebsd/share/man/man9/ |
H A D | atomic.9 | 305 depends on support for cache coherence in the underlying architecture. 306 In general, cache coherence on the default memory type, 310 For example, cache coherence is guaranteed on write-back memory by the 315 However, on some architectures, cache coherence might not be enabled on all 317 To determine if cache coherence is enabled for a non-default memory type,
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/freebsd/usr.sbin/nscd/ |
H A D | nscd.conf.5 | 75 the cache coherence. 96 This number should be kept low to avoid the cache coherence problems.
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/freebsd/contrib/llvm-project/clang/lib/Headers/ |
H A D | clwbintrin.h | 22 /// the cache coherence domain
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/freebsd/sys/contrib/device-tree/Bindings/perf/ |
H A D | marvell-cn10k-tad.yaml | 13 The Tag-and-Data units (TADs) maintain coherence and contain CN10K
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/freebsd/contrib/llvm-project/compiler-rt/lib/builtins/ |
H A D | clear_cache.c | 137 // is not required for instruction to data coherence. in __clear_cache() 147 // unification is not required for instruction to data coherence. in __clear_cache()
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/freebsd/sys/contrib/device-tree/src/powerpc/fsl/ |
H A D | e500v1_power_isa.dtsi | 45 power-isa-mmc; // Memory Coherence
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H A D | e500v2_power_isa.dtsi | 45 power-isa-mmc; // Memory Coherence
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H A D | e500mc_power_isa.dtsi | 53 power-isa-mmc; // Memory Coherence
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H A D | e5500_power_isa.dtsi | 53 power-isa-mmc; // Memory Coherence
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H A D | e6500_power_isa.dtsi | 53 power-isa-mmc; // Memory Coherence
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/freebsd/share/doc/smm/06.nfs/ |
H A D | ref.t | 59 Christopher. A. Kent, \fICache Coherence in Distributed Systems\fR,
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/freebsd/share/doc/smm/05.fastfs/ |
H A D | 6.t | 44 to the coherence of the paper.
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/freebsd/contrib/libcbor/doc/source/ |
H A D | development.rst | 7 Consistency and coherence are one of the key characteristics of good software.
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/freebsd/lib/libpmc/ |
H A D | pmc.atomsilvermont.3 | 171 Events that require a cache coherence qualifier to be specified use an
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H A D | pmc.core.3 | 159 Events that require a cache coherence qualifier to be specified use an
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H A D | pmc.atom.3 | 170 Events that require a cache coherence qualifier to be specified use an
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H A D | pmc.core2.3 | 169 Events that require a cache coherence qualifier to be specified use an
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/freebsd/sys/i386/i386/ |
H A D | pmap_base.c | 358 * coherence domain. in pmap_force_invalidate_cache_range()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | AMDKernelCodeT.h | 517 /// - MTYPE set to support memory coherence specified in
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H A D | SIMemoryLegalizer.cpp | 2698 // GFX12 specific, scope(desired coherence domain in cache hierarchy) is in expandStore()
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/freebsd/sys/cddl/contrib/opensolaris/uts/common/sys/ |
H A D | dtrace_impl.h | 274 * always be aligned to the coherence granularity -- generally 64 bytes.)
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/freebsd/sys/contrib/openzfs/module/os/freebsd/zfs/ |
H A D | zfs_vfsops.c | 1202 * This can cause a loss of coherence between ARC and page cache in zfs_domount()
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/freebsd/sys/riscv/riscv/ |
H A D | pmap.c | 994 * For SMP, these functions have to use IPIs for coherence. 4825 * required for data coherence. in pmap_page_set_memattr()
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/freebsd/share/examples/ipfilter/ |
H A D | ipf-howto.txt | 2791 I've never seen a class-C sized network with such coherence.
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/freebsd/sys/kern/ |
H A D | vfs_vnops.c | 2859 * use MAP_ASYNC to trade on-disk coherence for speed. in vn_mmap()
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