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/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dsamsung,exynos8895-clock.yaml21 CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
23 derived from CMU_TOP.
73 - description: CMU_FSYS0 BUS clock (from CMU_TOP)
74 - description: CMU_FSYS0 DPGTC clock (from CMU_TOP)
75 - description: CMU_FSYS0 MMC_EMBD clock (from CMU_TOP)
76 - description: CMU_FSYS0 UFS_EMBD clock (from CMU_TOP)
77 - description: CMU_FSYS0 USBDRD30 clock (from CMU_TOP)
99 - description: CMU_FSYS1 BUS clock (from CMU_TOP)
100 - description: CMU_FSYS1 PCIE clock (from CMU_TOP)
101 - description: CMU_FSYS1 UFS_CARD clock (from CMU_TOP)
[all …]
H A Dsamsung,exynos7885-clock.yaml23 CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
24 dividers; all other leaf clocks (other CMUs) are usually derived from CMU_TOP.
81 - description: CMU_CORE bus clock (from CMU_TOP)
82 - description: CCI clock (from CMU_TOP)
83 - description: G3D clock (from CMU_TOP)
103 - description: CMU_FSYS bus clock (from CMU_TOP)
104 - description: MMC_CARD clock (from CMU_TOP)
105 - description: MMC_EMBD clock (from CMU_TOP)
106 - description: MMC_SDIO clock (from CMU_TOP)
107 - description: USB30DRD clock (from CMU_TOP)
[all …]
H A Dsamsung,exynos850-clock.yaml23 CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
24 dividers; all other leaf clocks (other CMUs) are usually derived from CMU_TOP.
90 - description: CMU_APM bus clock (from CMU_TOP)
108 - description: AUD clock (from CMU_TOP)
144 - description: CMU_CORE bus clock (from CMU_TOP)
145 - description: CCI clock (from CMU_TOP)
146 - description: eMMC clock (from CMU_TOP)
147 - description: SSS clock (from CMU_TOP)
168 - description: CPUCL0 switch clock (from CMU_TOP)
169 - description: CPUCL0 debug clock (from CMU_TOP)
[all …]
H A Dsamsung,exynosautov920-clock.yaml23 CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
25 derived from CMU_TOP.
89 - description: CMU_CPUCL0 SWITCH clock (from CMU_TOP)
90 - description: CMU_CPUCL0 CLUSTER clock (from CMU_TOP)
91 - description: CMU_CPUCL0 DBG clock (from CMU_TOP)
112 - description: CMU_CPUCL1 SWITCH clock (from CMU_TOP)
113 - description: CMU_CPUCL1 CLUSTER clock (from CMU_TOP)
133 - description: CMU_CPUCL2 SWITCH clock (from CMU_TOP)
134 - description: CMU_CPUCL2 CLUSTER clock (from CMU_TOP)
155 - description: CMU_PERICn NOC clock (from CMU_TOP)
[all …]
H A Dsamsung,exynosautov9-clock.yaml23 CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
25 derived from CMU_TOP.
88 - description: CMU_BUSMC bus clock (from CMU_TOP)
106 - description: CMU_CORE bus clock (from CMU_TOP)
124 - description: DPU Main bus clock (from CMU_TOP)
142 - description: CMU_FSYS0 bus clock (from CMU_TOP)
143 - description: CMU_FSYS0 pcie clock (from CMU_TOP)
162 - description: CMU_FSYS1 bus clock (from CMU_TOP)
163 - description: CMU_FSYS1 mmc card clock (from CMU_TOP)
164 - description: CMU_FSYS1 usb clock (from CMU_TOP)
[all …]
H A Dexynos5433-clock.txt9 - "samsung,exynos5433-cmu-top" - clock controller compatible for CMU_TOP
201 cmu_top: clock-controller@10030000 {
265 <&cmu_top CLK_ACLK_FSYS_200>,
266 <&cmu_top CLK_SCLK_PCIE_100_FSYS>,
267 <&cmu_top CLK_SCLK_UFSUNIPRO_FSYS>,
268 <&cmu_top CLK_SCLK_MMC2_FSYS>,
269 <&cmu_top CLK_SCLK_MMC1_FSYS>,
270 <&cmu_top CLK_SCLK_MMC0_FSYS>,
271 <&cmu_top CLK_SCLK_USBHOST30_FSYS>,
272 <&cmu_top CLK_SCLK_USBDRD30_FSYS>;
[all …]
H A Dsamsung,exynos2200-cmu.yaml21 CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
23 derived from CMU_TOP.
77 - description: CMU_ALIVE NOC clock (from CMU_TOP)
95 - description: CMU_CMGP NOC clock (from CMU_TOP)
96 - description: CMU_CMGP PERI clock (from CMU_TOP)
116 - description: CMU_HSI0 NOC clock (from CMU_TOP)
117 - description: CMU_HSI0 DPGTC clock (from CMU_TOP)
118 - description: CMU_HSI0 DPOSC clock (from CMU_TOP)
119 - description: CMU_HSI0 USB32DRD clock (from CMU_TOP)
144 - description: CMU_PERICn NOC clock (from CMU_TOP)
[all …]
H A Dgoogle,gs101-clock.yaml19 CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
20 dividers; all other leaf clocks (other CMUs) are usually derived from CMU_TOP.
88 - description: HSI0 bus clock (from CMU_TOP)
89 - description: DPGTC (from CMU_TOP)
90 - description: USB DRD controller clock (from CMU_TOP)
91 - description: USB Display Port debug clock (from CMU_TOP)
113 - description: High Speed Interface bus clock (from CMU_TOP)
114 - description: High Speed Interface pcie clock (from CMU_TOP)
115 - description: High Speed Interface ufs clock (from CMU_TOP)
116 - description: High Speed Interface mmc clock (from CMU_TOP)
[all …]
H A Dsamsung,exynos990-clock.yaml21 CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
23 derived from CMU_TOP.
70 - description: CMU_HSI0 BUS clock (from CMU_TOP)
71 - description: CMU_HSI0 USB31DRD clock (from CMU_TOP)
72 - description: CMU_HSI0 USBDP_DEBUG clock (from CMU_TOP)
73 - description: CMU_HSI0 DPGTC clock (from CMU_TOP)
94 - description: CMU_PERIS BUS clock (from CMU_TOP)
129 <&cmu_top CLK_DOUT_CMU_HSI0_BUS>,
130 <&cmu_top CLK_DOUT_CMU_HSI0_USB31DRD>,
131 <&cmu_top CLK_DOUT_CMU_HSI0_USBDP_DEBUG>,
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/exynos/
H A Dexynos7885.dtsi199 <&cmu_top CLK_DOUT_PERI_BUS>,
200 <&cmu_top CLK_DOUT_PERI_SPI0>,
201 <&cmu_top CLK_DOUT_PERI_SPI1>,
202 <&cmu_top CLK_DOUT_PERI_UART0>,
203 <&cmu_top CLK_DOUT_PERI_UART1>,
204 <&cmu_top CLK_DOUT_PERI_UART2>,
205 <&cmu_top CLK_DOUT_PERI_USI0>,
206 <&cmu_top CLK_DOUT_PERI_USI1>,
207 <&cmu_top CLK_DOUT_PERI_USI2>;
226 <&cmu_top CLK_DOUT_CORE_BU
234 cmu_top: clock-controller@12060000 { global() label
[all...]
H A Dexynos2200.dtsi242 clocks = <&cmu_top CLK_DOUT_TCXO_DIV3>,
243 <&cmu_top CLK_DOUT_CMU_PERIS_NOC>,
244 <&cmu_top CLK_DOUT_CMU_PERIS_GIC>;
254 clocks = <&cmu_top CLK_DOUT_TCXO_DIV3>, <&cmu_peris CLK_MOUT_PERIS_GIC>;
301 <&cmu_top CLK_DOUT_CMU_PERIC0_NOC>,
302 <&cmu_top CLK_DOUT_CMU_PERIC0_IP0>,
303 <&cmu_top CLK_DOUT_CMU_PERIC0_IP1>;
323 <&cmu_top CLK_DOUT_CMU_PERIC1_NOC>,
324 <&cmu_top CLK_DOUT_CMU_PERIC1_IP0>,
325 <&cmu_top CLK_DOUT_CMU_PERIC1_IP1>;
[all …]
H A Dexynos5433-bus.dtsi12 clocks = <&cmu_top CLK_ACLK_G2D_400>;
20 clocks = <&cmu_top CLK_ACLK_G2D_266>;
28 clocks = <&cmu_top CLK_ACLK_GSCL_333>;
36 clocks = <&cmu_top CLK_ACLK_HEVC_400>;
44 clocks = <&cmu_top CLK_SCLK_JPEG_MSCL>;
52 clocks = <&cmu_top CLK_ACLK_MFC_400>;
60 clocks = <&cmu_top CLK_ACLK_MSCL_400>;
68 clocks = <&cmu_top CLK_ACLK_BUS0_400>;
76 clocks = <&cmu_top CLK_ACLK_BUS1_400>;
H A Dexynos5433-tm2-common.dtsi228 <&cmu_top CLK_MOUT_AUD_PLL>,
229 <&cmu_top CLK_MOUT_AUD_PLL_USER_T>,
230 <&cmu_top CLK_MOUT_SCLK_AUDIO0>,
231 <&cmu_top CLK_MOUT_SCLK_AUDIO1>,
232 <&cmu_top CLK_MOUT_SCLK_SPDIF>,
241 <&cmu_top CLK_DIV_SCLK_AUDIO0>,
242 <&cmu_top CLK_DIV_SCLK_AUDIO1>,
243 <&cmu_top CLK_DIV_SCLK_PCM1>,
244 <&cmu_top CLK_DIV_SCLK_I2S1>;
246 assigned-clock-parents = <&cmu_top CLK_FOUT_AUD_PLL>,
[all …]
H A Dexynos850.dtsi254 clocks = <&oscclk>, <&cmu_top CLK_DOUT_PERI_BUS>,
255 <&cmu_top CLK_DOUT_PERI_UART>,
256 <&cmu_top CLK_DOUT_PERI_IP>;
266 clocks = <&oscclk>, <&cmu_top CLK_DOUT_CPUCL1_SWITCH>,
267 <&cmu_top CLK_DOUT_CPUCL1_DBG>;
277 clocks = <&oscclk>, <&cmu_top CLK_DOUT_CPUCL0_SWITCH>,
278 <&cmu_top CLK_DOUT_CPUCL0_DBG>;
288 clocks = <&oscclk>, <&cmu_top CLK_DOUT_G3D_SWITCH>;
297 clocks = <&oscclk>, <&cmu_top CLK_DOUT_CLKCMU_APM_BUS>;
315 clocks = <&oscclk>, <&cmu_top CLK_DOUT_CORE_BUS>,
[all …]
H A Dexynos8895.dtsi178 <&cmu_top CLK_DOUT_CMU_PERIS_BUS>;
221 <&cmu_top CLK_DOUT_CMU_PERIC0_BUS>,
222 <&cmu_top CLK_DOUT_CMU_PERIC0_UART_DBG>,
223 <&cmu_top CLK_DOUT_CMU_PERIC0_USI00>,
224 <&cmu_top CLK_DOUT_CMU_PERIC0_USI01>,
225 <&cmu_top CLK_DOUT_CMU_PERIC0_USI02>,
226 <&cmu_top CLK_DOUT_CMU_PERIC0_USI03>;
509 <&cmu_top CLK_DOUT_CMU_PERIC1_BUS>,
510 <&cmu_top CLK_DOUT_CMU_PERIC1_SPEEDY2>,
511 <&cmu_top CLK_DOUT_CMU_PERIC1_SPI_CAM0>,
[all …]
H A Dexynos5433.dtsi369 cmu_top: clock-controller@10030000 { label
433 <&cmu_top CLK_ACLK_FSYS_200>,
434 <&cmu_top CLK_SCLK_PCIE_100_FSYS>,
435 <&cmu_top CLK_SCLK_UFSUNIPRO_FSYS>,
436 <&cmu_top CLK_SCLK_MMC2_FSYS>,
437 <&cmu_top CLK_SCLK_MMC1_FSYS>,
438 <&cmu_top CLK_SCLK_MMC0_FSYS>,
439 <&cmu_top CLK_SCLK_USBHOST30_FSYS>,
440 <&cmu_top CLK_SCLK_USBDRD30_FSYS>;
452 <&cmu_top CLK_ACLK_G2D_266>,
[all …]
H A Dexynos990.dtsi190 <&cmu_top CLK_DOUT_CMU_PERIS_BUS>;
246 <&cmu_top CLK_DOUT_CMU_HSI0_BUS>,
247 <&cmu_top CLK_DOUT_CMU_HSI0_USB31DRD>,
248 <&cmu_top CLK_DOUT_CMU_HSI0_USBDP_DEBUG>,
249 <&cmu_top CLK_DOUT_CMU_HSI0_DPGTC>;
304 cmu_top: clock-controller@1a330000 { label
H A Dexynosautov920.dtsi308 <&cmu_top DOUT_CLKCMU_MISC_NOC>;
412 <&cmu_top DOUT_CLKCMU_PERIC0_NOC>,
413 <&cmu_top DOUT_CLKCMU_PERIC0_IP>;
890 <&cmu_top DOUT_CLKCMU_PERIC1_NOC>,
891 <&cmu_top DOUT_CLKCMU_PERIC1_IP>;
1350 cmu_top: clock-controller@11000000 { label
1380 <&cmu_top DOUT_CLKCMU_HSI0_NOC>;
1397 <&cmu_top DOUT_CLKCMU_HSI1_NOC>,
1398 <&cmu_top DOUT_CLKCMU_HSI1_USBDRD>,
1399 <&cmu_top DOUT_CLKCMU_HSI1_MMC_CARD>;
[all …]
H A Dexynos2200-g0s.dts98 <&cmu_top CLK_DOUT_CMU_HSI0_NOC>,
99 <&cmu_top CLK_DOUT_CMU_HSI0_DPGTC>,
100 <&cmu_top CLK_DOUT_CMU_HSI0_DPOSC>,
101 <&cmu_top CLK_DOUT_CMU_HSI0_USB32DRD>;
H A Dexynosautov9.dtsi180 <&cmu_top DOUT_CLKCMU_PERIS_BUS>;
191 <&cmu_top DOUT_CLKCMU_PERIC0_BUS>,
192 <&cmu_top DOUT_CLKCMU_PERIC0_IP>;
204 <&cmu_top DOUT_CLKCMU_PERIC1_BUS>,
205 <&cmu_top DOUT_CLKCMU_PERIC1_IP>;
217 <&cmu_top DOUT_CLKCMU_FSYS1_BUS>,
218 <&cmu_top GOUT_CLKCMU_FSYS1_MMC_CARD>,
219 <&cmu_top DOUT_CLKCMU_FSYS1_USBDRD>;
232 <&cmu_top DOUT_CLKCMU_FSYS0_BUS>,
233 <&cmu_top DOUT_CLKCMU_FSYS0_PCIE>;
[all …]
H A Dexynos850-e850-96.dts172 <&cmu_top CLK_DOUT_HSI_BUS>,
173 <&cmu_top CLK_DOUT_HSI_MMC_CARD>,
174 <&cmu_top CLK_DOUT_HSI_USB20DRD>;
/freebsd/sys/contrib/device-tree/include/dt-bindings/clock/
H A Dsamsung,exynosautov9.h12 /* CMU_TOP */
19 /* MUX in CMU_TOP */
68 /* DIV in CMU_TOP */
120 /* GAT in CMU_TOP */
H A Dsamsung,exynosautov920.h12 /* CMU_TOP */
21 /* MUX in CMU_TOP */
85 /* DIV in CMU_TOP */
H A Dgoogle,gs101.h12 /* CMU_TOP PLL */
19 /* CMU_TOP MUX */
93 /* CMU_TOP Dividers */
168 /* CMU_TOP Gates */
/freebsd/sys/contrib/device-tree/src/arm64/exynos/google/
H A Dgs101.dtsi293 clocks = <&cmu_top CLK_DOUT_CMU_MISC_BUS>,
294 <&cmu_top CLK_DOUT_CMU_MISC_SSS>;
370 <&cmu_top CLK_DOUT_CMU_PERIC0_BUS>,
371 <&cmu_top CLK_DOUT_CMU_PERIC0_IP>;
916 <&cmu_top CLK_DOUT_CMU_PERIC1_BUS>,
917 <&cmu_top CLK_DOUT_CMU_PERIC1_IP>;
1271 <&cmu_top CLK_DOUT_CMU_HSI0_BUS>,
1272 <&cmu_top CLK_DOUT_CMU_HSI0_DPGTC>,
1273 <&cmu_top CLK_DOUT_CMU_HSI0_USB31DRD>,
1274 <&cmu_top CLK_DOUT_CMU_HSI0_USBDPDBG>;
[all …]

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