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/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dsamsung,exynos7885-clock.yaml23 CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
24 dividers; all other leaf clocks (other CMUs) are usually derived from CMU_TOP.
81 - description: CMU_CORE bus clock (from CMU_TOP)
82 - description: CCI clock (from CMU_TOP)
83 - description: G3D clock (from CMU_TOP)
103 - description: CMU_FSYS bus clock (from CMU_TOP)
104 - description: MMC_CARD clock (from CMU_TOP)
105 - description: MMC_EMBD clock (from CMU_TOP)
106 - description: MMC_SDIO clock (from CMU_TOP)
107 - description: USB30DRD clock (from CMU_TOP)
[all …]
H A Dsamsung,exynos850-clock.yaml23 CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
24 dividers; all other leaf clocks (other CMUs) are usually derived from CMU_TOP.
90 - description: CMU_APM bus clock (from CMU_TOP)
108 - description: AUD clock (from CMU_TOP)
144 - description: CMU_CORE bus clock (from CMU_TOP)
145 - description: CCI clock (from CMU_TOP)
146 - description: eMMC clock (from CMU_TOP)
147 - description: SSS clock (from CMU_TOP)
168 - description: CPUCL0 switch clock (from CMU_TOP)
169 - description: CPUCL0 debug clock (from CMU_TOP)
[all …]
H A Dsamsung,exynosautov9-clock.yaml23 CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
25 derived from CMU_TOP.
88 - description: CMU_BUSMC bus clock (from CMU_TOP)
106 - description: CMU_CORE bus clock (from CMU_TOP)
124 - description: DPU Main bus clock (from CMU_TOP)
142 - description: CMU_FSYS0 bus clock (from CMU_TOP)
143 - description: CMU_FSYS0 pcie clock (from CMU_TOP)
162 - description: CMU_FSYS1 bus clock (from CMU_TOP)
163 - description: CMU_FSYS1 mmc card clock (from CMU_TOP)
164 - description: CMU_FSYS1 usb clock (from CMU_TOP)
[all …]
H A Dexynos5433-clock.txt9 - "samsung,exynos5433-cmu-top" - clock controller compatible for CMU_TOP
201 cmu_top: clock-controller@10030000 {
265 <&cmu_top CLK_ACLK_FSYS_200>,
266 <&cmu_top CLK_SCLK_PCIE_100_FSYS>,
267 <&cmu_top CLK_SCLK_UFSUNIPRO_FSYS>,
268 <&cmu_top CLK_SCLK_MMC2_FSYS>,
269 <&cmu_top CLK_SCLK_MMC1_FSYS>,
270 <&cmu_top CLK_SCLK_MMC0_FSYS>,
271 <&cmu_top CLK_SCLK_USBHOST30_FSYS>,
272 <&cmu_top CLK_SCLK_USBDRD30_FSYS>;
[all …]
H A Dgoogle,gs101-clock.yaml19 CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
20 dividers; all other leaf clocks (other CMUs) are usually derived from CMU_TOP.
88 - description: HSI0 bus clock (from CMU_TOP)
89 - description: DPGTC (from CMU_TOP)
90 - description: USB DRD controller clock (from CMU_TOP)
91 - description: USB Display Port debug clock (from CMU_TOP)
113 - description: High Speed Interface bus clock (from CMU_TOP)
114 - description: High Speed Interface pcie clock (from CMU_TOP)
115 - description: High Speed Interface ufs clock (from CMU_TOP)
116 - description: High Speed Interface mmc clock (from CMU_TOP)
[all …]
H A Dsamsung,exynosautov920-clock.yaml22 CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
24 derived from CMU_TOP.
85 - description: CMU_PERICn NOC clock (from CMU_TOP)
86 - description: CMU_PERICn IP clock (from CMU_TOP)
106 - description: CMU_MISC/CMU_HSI0 NOC clock (from CMU_TOP)
124 - description: CMU_HSI1 NOC clock (from CMU_TOP)
125 - description: CMU_HSI1 USBDRD clock (from CMU_TOP)
126 - description: CMU_HSI1 MMC_CARD clock (from CMU_TOP)
155 <&cmu_top DOUT_CLKCMU_PERIC0_NOC>,
156 <&cmu_top DOUT_CLKCMU_PERIC0_IP>;
H A Dsamsung,exynos5433-clock.yaml26 # CMU_TOP which generates clocks for
/freebsd/sys/contrib/device-tree/src/arm64/exynos/
H A Dexynos7885.dtsi199 <&cmu_top CLK_DOUT_PERI_BUS>,
200 <&cmu_top CLK_DOUT_PERI_SPI0>,
201 <&cmu_top CLK_DOUT_PERI_SPI1>,
202 <&cmu_top CLK_DOUT_PERI_UART0>,
203 <&cmu_top CLK_DOUT_PERI_UART1>,
204 <&cmu_top CLK_DOUT_PERI_UART2>,
205 <&cmu_top CLK_DOUT_PERI_USI0>,
206 <&cmu_top CLK_DOUT_PERI_USI1>,
207 <&cmu_top CLK_DOUT_PERI_USI2>;
226 <&cmu_top CLK_DOUT_CORE_BU
234 cmu_top: clock-controller@12060000 { global() label
[all...]
H A Dexynos5433-bus.dtsi12 clocks = <&cmu_top CLK_ACLK_G2D_400>;
20 clocks = <&cmu_top CLK_ACLK_G2D_266>;
28 clocks = <&cmu_top CLK_ACLK_GSCL_333>;
36 clocks = <&cmu_top CLK_ACLK_HEVC_400>;
44 clocks = <&cmu_top CLK_SCLK_JPEG_MSCL>;
52 clocks = <&cmu_top CLK_ACLK_MFC_400>;
60 clocks = <&cmu_top CLK_ACLK_MSCL_400>;
68 clocks = <&cmu_top CLK_ACLK_BUS0_400>;
76 clocks = <&cmu_top CLK_ACLK_BUS1_400>;
H A Dexynos5433-tm2-common.dtsi228 <&cmu_top CLK_MOUT_AUD_PLL>,
229 <&cmu_top CLK_MOUT_AUD_PLL_USER_T>,
230 <&cmu_top CLK_MOUT_SCLK_AUDIO0>,
231 <&cmu_top CLK_MOUT_SCLK_AUDIO1>,
232 <&cmu_top CLK_MOUT_SCLK_SPDIF>,
241 <&cmu_top CLK_DIV_SCLK_AUDIO0>,
242 <&cmu_top CLK_DIV_SCLK_AUDIO1>,
243 <&cmu_top CLK_DIV_SCLK_PCM1>,
244 <&cmu_top CLK_DIV_SCLK_I2S1>;
246 assigned-clock-parents = <&cmu_top CLK_FOUT_AUD_PL
[all...]
H A Dexynos850.dtsi254 clocks = <&oscclk>, <&cmu_top CLK_DOUT_PERI_BUS>,
255 <&cmu_top CLK_DOUT_PERI_UART>,
256 <&cmu_top CLK_DOUT_PERI_IP>;
266 clocks = <&oscclk>, <&cmu_top CLK_DOUT_CPUCL1_SWITCH>,
267 <&cmu_top CLK_DOUT_CPUCL1_DBG>;
277 clocks = <&oscclk>, <&cmu_top CLK_DOUT_CPUCL0_SWITCH>,
278 <&cmu_top CLK_DOUT_CPUCL0_DBG>;
288 clocks = <&oscclk>, <&cmu_top CLK_DOUT_G3D_SWITCH>;
297 clocks = <&oscclk>, <&cmu_top CLK_DOUT_CLKCMU_APM_BUS>;
315 clocks = <&oscclk>, <&cmu_top CLK_DOUT_CORE_BUS>,
[all …]
H A Dexynos5433.dtsi369 cmu_top: clock-controller@10030000 { label
433 <&cmu_top CLK_ACLK_FSYS_200>,
434 <&cmu_top CLK_SCLK_PCIE_100_FSYS>,
435 <&cmu_top CLK_SCLK_UFSUNIPRO_FSYS>,
436 <&cmu_top CLK_SCLK_MMC2_FSYS>,
437 <&cmu_top CLK_SCLK_MMC1_FSYS>,
438 <&cmu_top CLK_SCLK_MMC0_FSYS>,
439 <&cmu_top CLK_SCLK_USBHOST30_FSYS>,
440 <&cmu_top CLK_SCLK_USBDRD30_FSYS>;
452 <&cmu_top CLK_ACLK_G2D_266>,
[all …]
H A Dexynosautov9.dtsi180 <&cmu_top DOUT_CLKCMU_PERIS_BUS>;
191 <&cmu_top DOUT_CLKCMU_PERIC0_BUS>,
192 <&cmu_top DOUT_CLKCMU_PERIC0_IP>;
204 <&cmu_top DOUT_CLKCMU_PERIC1_BUS>,
205 <&cmu_top DOUT_CLKCMU_PERIC1_IP>;
217 <&cmu_top DOUT_CLKCMU_FSYS1_BUS>,
218 <&cmu_top GOUT_CLKCMU_FSYS1_MMC_CARD>,
219 <&cmu_top DOUT_CLKCMU_FSYS1_USBDRD>;
232 <&cmu_top DOUT_CLKCMU_FSYS0_BUS>,
233 <&cmu_top DOUT_CLKCMU_FSYS0_PCIE>;
[all …]
H A Dexynos850-e850-96.dts175 <&cmu_top CLK_DOUT_HSI_BUS>,
176 <&cmu_top CLK_DOUT_HSI_MMC_CARD>,
177 <&cmu_top CLK_DOUT_HSI_USB20DRD>;
H A Dexynosautov920.dtsi191 <&cmu_top DOUT_CLKCMU_PERIC0_NOC>,
192 <&cmu_top DOUT_CLKCMU_PERIC0_IP>;
262 cmu_top: clock-controller@11000000 { label
/freebsd/sys/contrib/device-tree/include/dt-bindings/clock/
H A Dsamsung,exynosautov9.h12 /* CMU_TOP */
19 /* MUX in CMU_TOP */
68 /* DIV in CMU_TOP */
120 /* GAT in CMU_TOP */
H A Dsamsung,exynosautov920.h12 /* CMU_TOP */
21 /* MUX in CMU_TOP */
85 /* DIV in CMU_TOP */
H A Dgoogle,gs101.h12 /* CMU_TOP PLL */
19 /* CMU_TOP MUX */
93 /* CMU_TOP Dividers */
168 /* CMU_TOP Gates */
H A Dexynos7885.h11 /* CMU_TOP */
H A Dexynos850.h12 /* CMU_TOP */
H A Dexynos5260-clk.h14 /* List Of Clocks For CMU_TOP */
H A Dexynos5433.h10 /* CMU_TOP */
/freebsd/sys/contrib/device-tree/src/arm64/exynos/google/
H A Dgs101.dtsi282 clocks = <&cmu_top CLK_DOUT_CMU_MISC_BUS>,
283 <&cmu_top CLK_DOUT_CMU_MISC_SSS>;
359 <&cmu_top CLK_DOUT_CMU_PERIC0_BUS>,
360 <&cmu_top CLK_DOUT_CMU_PERIC0_IP>;
905 <&cmu_top CLK_DOUT_CMU_PERIC1_BUS>,
906 <&cmu_top CLK_DOUT_CMU_PERIC1_IP>;
1260 <&cmu_top CLK_DOUT_CMU_HSI0_BUS>,
1261 <&cmu_top CLK_DOUT_CMU_HSI0_DPGTC>,
1262 <&cmu_top CLK_DOUT_CMU_HSI0_USB31DRD>,
1263 <&cmu_top CLK_DOUT_CMU_HSI0_USBDPDBG>;
[all …]