Searched full:cmu_peric0 (Results 1 – 11 of 11) sorted by relevance
123 - description: CMU_PERIC0 BUS clock (from CMU_TOP)124 - description: CMU_PERIC0 UART_DBG clock (from CMU_TOP)125 - description: CMU_PERIC0 USI00 clock (from CMU_TOP)126 - description: CMU_PERIC0 USI01 clock (from CMU_TOP)127 - description: CMU_PERIC0 USI02 clock (from CMU_TOP)128 - description: CMU_PERIC0 USI03 clock (from CMU_TOP)
220 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0>,221 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0>;
266 /* CMU_PERIC0 */
241 /* CMU_PERIC0 */
360 /* CMU_PERIC0 */
1592 /* ---- CMU_PERIC0 --------------------------------------------------------- */1594 /* Register Offset definitions for CMU_PERIC0 (0x10200000) */1679 /* List of parent clocks for Muxes in CMU_PERIC0 */
1348 /* ---- CMU_PERIC0 --------------------------------------------------------- */1350 /* Register Offset definitions for CMU_PERIC0 (0x10800000) */1403 /* List of parent clocks for Muxes in CMU_PERIC0 */
1355 /* ---- CMU_PERIC0 --------------------------------------------------------- */1357 /* Register Offset definitions for CMU_PERIC0 (0x10400000) */1546 /* Parent clock list for CMU_PERIC0 muxes */
2127 /* ---- CMU_PERIC0 ---------------------------------------------------------- */2129 /* Register Offset definitions for CMU_PERIC0 (0x10400000) */2196 /* List of parent clocks for Muxes in CMU_PERIC0 */
3756 /* ---- CMU_PERIC0 ---------------------------------------------------------- */3758 /* Register Offset definitions for CMU_PERIC0 (0x10800000) */4017 /* List of parent clocks for Muxes in CMU_PERIC0 */
2885 /* ---- CMU_PERIC0 --------------------------------------------------------- */2887 /* Register Offset definitions for CMU_PERIC0 (0x10400000) */