Home
last modified time | relevance | path

Searched full:cmu_peric0 (Results 1 – 14 of 14) sorted by relevance

/linux/arch/arm64/boot/dts/exynos/
H A Dexynosautov9.dtsi185 cmu_peric0: clock-controller@10200000 { label
449 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_0>,
450 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_0>;
461 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_0>,
462 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_0>;
474 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_0>,
475 <&cmu_peric0 CLK_DOUT_PERIC0_USI00_USI>,
476 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_0>;
494 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_0>,
495 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_0>;
[all …]
/linux/Documentation/devicetree/bindings/clock/
H A Dsamsung,exynos8895-clock.yaml123 - description: CMU_PERIC0 BUS clock (from CMU_TOP)
124 - description: CMU_PERIC0 UART_DBG clock (from CMU_TOP)
125 - description: CMU_PERIC0 USI00 clock (from CMU_TOP)
126 - description: CMU_PERIC0 USI01 clock (from CMU_TOP)
127 - description: CMU_PERIC0 USI02 clock (from CMU_TOP)
128 - description: CMU_PERIC0 USI03 clock (from CMU_TOP)
H A Dsamsung,exynosautov920-clock.yaml145 # Clock controller node for CMU_PERIC0
149 cmu_peric0: clock-controller@10800000 {
H A Dsamsung,exynosautov9-clock.yaml206 - description: CMU_PERIC0 bus clock (from CMU_TOP)
/linux/Documentation/devicetree/bindings/serial/
H A Dsamsung_uart.yaml210 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0>,
211 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0>;
/linux/include/dt-bindings/clock/
H A Dsamsung,exynosautov920.h165 /* CMU_PERIC0 */
H A Dsamsung,exynosautov9.h266 /* CMU_PERIC0 */
H A Dsamsung,exynos8895.h360 /* CMU_PERIC0 */
H A Dgoogle,gs101.h508 /* CMU_PERIC0 */
/linux/drivers/clk/samsung/
H A Dclk-exynosautov920.c1008 /* ---- CMU_PERIC0 --------------------------------------------------------- */
1010 /* Register Offset definitions for CMU_PERIC0 (0x10800000) */
1063 /* List of parent clocks for Muxes in CMU_PERIC0 */
H A Dclk-exynosautov9.c1593 /* ---- CMU_PERIC0 --------------------------------------------------------- */
1595 /* Register Offset definitions for CMU_PERIC0 (0x10200000) */
1680 /* List of parent clocks for Muxes in CMU_PERIC0 */
H A Dclk-exynos7.c629 /* Register Offset definitions for CMU_PERIC0 (0x13610000) */
634 /* List of parent clocks for Muxes in CMU_PERIC0 */
H A Dclk-exynos8895.c2128 /* ---- CMU_PERIC0 ---------------------------------------------------------- */
2130 /* Register Offset definitions for CMU_PERIC0 (0x10400000) */
2197 /* List of parent clocks for Muxes in CMU_PERIC0 */
H A Dclk-gs101.c3438 /* ---- CMU_PERIC0 ---------------------------------------------------------- */
3440 /* Register Offset definitions for CMU_PERIC0 (0x10800000) */
3699 /* List of parent clocks for Muxes in CMU_PERIC0 */