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Searched full:cmu_mif (Results 1 – 9 of 9) sorted by relevance

/linux/arch/arm64/boot/dts/exynos/
H A Dexynos7870.dtsi156 <&cmu_mif CLK_GOUT_MIF_CMU_PERI_BUS>,
157 <&cmu_mif CLK_GOUT_MIF_CMU_PERI_SPI0>,
158 <&cmu_mif CLK_GOUT_MIF_CMU_PERI_SPI1>,
159 <&cmu_mif CLK_GOUT_MIF_CMU_PERI_SPI2>,
160 <&cmu_mif CLK_GOUT_MIF_CMU_PERI_SPI3>,
161 <&cmu_mif CLK_GOUT_MIF_CMU_PERI_SPI4>,
162 <&cmu_mif CLK_GOUT_MIF_CMU_PERI_UART0>,
163 <&cmu_mif CLK_GOUT_MIF_CMU_PERI_UART1>,
164 <&cmu_mif CLK_GOUT_MIF_CMU_PERI_UART2>;
167 cmu_mif: clock-controller@10460000 { label
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H A Dexynos5433-tm2.dts26 <&cmu_mif CLK_DIV_SCLK_DECON_TV_ECLK>,
35 <&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>,
40 <&cmu_mif CLK_ACLK_DISP_333>,
41 <&cmu_mif CLK_SCLK_DSIM0_DISP>,
43 <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>,
48 <&cmu_mif CLK_MOUT_BUS_PLL_DIV2>,
49 <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
51 <&cmu_mif CLK_SCLK_DSD_DISP>;
H A Dexynos5433-tm2e.dts26 <&cmu_mif CLK_DIV_SCLK_DECON_TV_ECLK>,
35 <&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>,
39 <&cmu_mif CLK_ACLK_DISP_333>,
40 <&cmu_mif CLK_SCLK_DSIM0_DISP>,
42 <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>,
47 <&cmu_mif CLK_MOUT_BUS_PLL_DIV2>,
48 <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
H A Dexynos5433-bus.dtsi84 clocks = <&cmu_mif CLK_ACLK_BUS2_400>;
H A Dexynos5433-tm2-common.dtsi296 &cmu_mif {
297 assigned-clocks = <&cmu_mif CLK_MOUT_SCLK_DSD_A>, <&cmu_mif CLK_DIV_SCLK_DSD>;
298 assigned-clock-parents = <&cmu_mif CLK_MOUT_MFC_PLL_DIV2>;
/linux/Documentation/devicetree/bindings/clock/
H A Dsamsung,exynos5433-clock.yaml32 # CMU_MIF which generates clocks for DRAM Memory Controller domain
522 <&cmu_mif CLK_SCLK_MFC_PLL>,
523 <&cmu_mif CLK_SCLK_BUS_PLL>;
/linux/include/dt-bindings/clock/
H A Dexynos5260-clk.h168 /* List Of Clocks For CMU_MIF */
H A Dexynos5433.h201 /* CMU_MIF */
/linux/drivers/clk/samsung/
H A Dclk-exynos5260.h282 *Registers for CMU_MIF