Searched full:cmu_fsys1 (Results 1 – 10 of 10) sorted by relevance
99 - description: CMU_FSYS1 BUS clock (from CMU_TOP)100 - description: CMU_FSYS1 PCIE clock (from CMU_TOP)101 - description: CMU_FSYS1 UFS_CARD clock (from CMU_TOP)102 - description: CMU_FSYS1 MMC_CARD clock (from CMU_TOP)226 cmu_fsys1: clock-controller@11400000 {
162 - description: CMU_FSYS1 bus clock (from CMU_TOP)163 - description: CMU_FSYS1 mmc card clock (from CMU_TOP)164 - description: CMU_FSYS1 usb clock (from CMU_TOP)
181 # Clock controller node for CMU_FSYS1
234 /* CMU_FSYS1 */
314 /* CMU_FSYS1 */
541 * This clock is required for the CMU_FSYS1 registers access, keep it985 /* Register Offset definitions for CMU_FSYS1 (0x156E0000) */997 * List of parent clocks for Muxes in CMU_FSYS1
1399 /* ---- CMU_FSYS1 ---------------------------------------------------------- */1401 /* Register Offset definitions for CMU_FSYS1 (0x17040000) */1435 /* List of parent clocks for Muxes in CMU_FSYS1 */
1829 /* ---- CMU_FSYS1 ---------------------------------------------------------- */1831 /* Register Offset definitions for CMU_FSYS1 (0x11400000) */1932 /* List of parent clocks for Muxes in CMU_FSYS1 */
982 /* Register Offset definitions for CMU_FSYS1 (0x16810000) */1054 /* List of parent clocks for Muxes in CMU_FSYS1 */
211 cmu_fsys1: clock-controller@17040000 { label