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Searched full:cmu_aud (Results 1 – 12 of 12) sorted by relevance

/linux/Documentation/devicetree/bindings/mfd/
H A Dsamsung,exynos5433-lpass.yaml68 clocks = <&cmu_aud CLK_PCLK_SFR0_CTRL>;
79 clocks = <&cmu_aud CLK_ACLK_DMAC>;
95 clocks = <&cmu_aud CLK_PCLK_AUD_I2S>,
96 <&cmu_aud CLK_SCLK_AUD_I2S>,
97 <&cmu_aud CLK_SCLK_I2S_BCLK>;
110 clocks = <&cmu_aud CLK_PCLK_AUD_UART>,
111 <&cmu_aud CLK_SCLK_AUD_UART>;
/linux/arch/arm64/boot/dts/exynos/
H A Dexynos5433-tm2-common.dtsi224 &cmu_aud {
225 assigned-clocks = <&cmu_aud CLK_MOUT_AUD_PLL_USER>,
226 <&cmu_aud CLK_MOUT_SCLK_AUD_I2S>,
227 <&cmu_aud CLK_MOUT_SCLK_AUD_PCM>,
234 <&cmu_aud CLK_DIV_AUD_CA5>,
235 <&cmu_aud CLK_DIV_ACLK_AUD>,
236 <&cmu_aud CLK_DIV_PCLK_DBG_AUD>,
237 <&cmu_aud CLK_DIV_SCLK_AUD_I2S>,
238 <&cmu_aud CLK_DIV_SCLK_AUD_PCM>,
239 <&cmu_aud CLK_DIV_SCLK_AUD_SLIMBUS>,
[all …]
H A Dexynos5433.dtsi483 cmu_aud: clock-controller@114c0000 { label
1904 clocks = <&cmu_aud CLK_PCLK_SFR0_CTRL>;
1915 clocks = <&cmu_aud CLK_ACLK_DMAC>;
1930 clocks = <&cmu_aud CLK_PCLK_AUD_I2S>,
1931 <&cmu_aud CLK_SCLK_AUD_I2S>,
1932 <&cmu_aud CLK_SCLK_I2S_BCLK>;
1946 clocks = <&cmu_aud CLK_PCLK_AUD_UART>,
1947 <&cmu_aud CLK_SCLK_AUD_UART>;
H A Dexynos850.dtsi384 cmu_aud: clock-controller@14a00000 { label
602 clocks = <&cmu_aud CLK_GOUT_AUD_SYSMMU_CLK>;
/linux/include/dt-bindings/clock/
H A Dexynos850.h130 /* CMU_AUD */
H A Dexynos5260-clk.h207 /* List Of Clocks For CMU_AUD */
H A Dexynos5433.h760 /* CMU_AUD */
/linux/drivers/clk/samsung/
H A Dclk-exynos5260.h13 *Registers for CMU_AUD
H A Dclk-exynos7.c1229 /* Register Offset definitions for CMU_AUD (0x114C0000) */
1238 * List of parent clocks for Muxes in CMU_AUD
H A Dclk-exynos850.c250 /* List of parent clocks for Muxes in CMU_TOP: for CMU_AUD */
718 /* ---- CMU_AUD ------------------------------------------------------------- */
832 /* List of parent clocks for Muxes in CMU_AUD */
H A Dclk-exynos5260.c91 /* CMU_AUD */
H A Dclk-exynos5433.c2922 * Register offset definitions for CMU_AUD