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/linux/Documentation/devicetree/bindings/perf/
H A Darm,cmn.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/perf/arm,cmn.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Arm CMN (Coherent Mesh Network) Performance Monitors
11 - Robin Murphy <robin.murphy@arm.com>
16 - arm,cmn-600
17 - arm,cmn-650
18 - arm,cmn-700
19 - arm,cmn-s3
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/linux/Documentation/admin-guide/perf/
H A Darm-cmn.rst5 CMN-600 is a configurable mesh interconnect consisting of a rectangular
9 CMN implements a distributed PMU design as part of its debug and trace
17 ----------
20 see /sys/bus/event_source/devices/arm_cmn_0. Multi-chip systems may link
21 more than one CMN together via external CCIX links - in this situation,
26 definitions - "type" selects the respective node type, and "eventid" the
30 * Since RN-D nodes do not have any distinct events from RN-I nodes, they
44 "nodeid" to the appropriate value derived from the CMN configuration
48 -----------
61 REQ or SNP channel, it can be specified as two events - one for each
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/linux/drivers/perf/
H A Darm-cmn.c1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (C) 2016-2020 Arm Limited
3 // ARM CMN/CI interconnect PMU driver
11 #include <linux/io-64-nonatomic-lo-hi.h>
36 #define CMN_MAX_DTMS (CMN_MAX_XPS + (CMN_MAX_DIMENSION - 1) * 4)
128 /* DTC counters are paired in 64-bit registers on a 16-byte stride. Yuck */
130 #define CMN_DT_PMEVCNT(dtc, n) ((dtc)->pmu_base + _CMN_DT_CNT_REG(n))
131 #define CMN_DT_PMCCNTR(dtc) ((dtc)->pmu_base + 0x40)
133 #define CMN_DT_PMEVCNTSR(dtc, n) ((dtc)->pmu_base + 0x50 + _CMN_DT_CNT_REG(n))
134 #define CMN_DT_PMCCNTRSR(dtc) ((dtc)->pmu_base + 0x90)
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
17 If compiled as a module, it will be called arm-cci.
20 bool "support CCI-400"
25 CCI-400 provides 4 independent event counters counting events related
29 bool "support CCI-500/CCI-550"
33 CCI-500/CCI-550 both provide 8 independent event counters, which can
45 tristate "Arm CMN-600 PMU support"
48 Support for PMU events monitoring on the Arm CMN-600 Coherent Mesh
52 tristate "Arm NI-700 PMU support"
55 Support for PMU events monitoring on the Arm NI-700 Network-on-Chip
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