cluster\-mode (full) in projects: freebsd

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/freebsd/lib/libpmc/pmu-events/arch/s390/cf_z14/
H A D	extended.json	5 "BriefDescription": "L1D Read-only Exclusive Writes", 6 …blicDescription": "A directory write to the Level-1 Data cache where the line was originally in a … 18 …data cache. Incremented by one for every TLB2 miss in progress for the Level-1 Data cache on this … 23 "BriefDescription": "DTLB2 One-Megabyte Page Writes", 24 … into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte page… 29 "BriefDescription": "DTLB2 Two-Gigabyte Page Writes", 30 …"PublicDescription": "A translation entry for a two-gigabyte page was written into the Level-2 TLB" 36 …on": "A directory write to the Level-1 Data cache directory where the returned cache line was sour… 48 …tion cache. Incremented by one for every TLB2 miss in progress for the Level-1 Instruction cache i… 54 … "A directory write to the Level-1 Instruction cache directory where the returned cache line was s… [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/icelakex/
H A D	other.json	3 … where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule.", 9 …s running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX… 21 … running with power-delivery for license level 1. This includes high current AVX 256-bit instruct… 33 … running with power-delivery for license level 2 (introduced in Skylake Server microarchtecture). … 145 …t, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are con… 156 … on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.", 189 …t, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are con… 200 …et, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those PMM accesses that are con… 244 … on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.", 255 … on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.", [all …]
H A D	cache.json	9 …opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.", 59 …-demand loads and gets hit at least once by demand. The valid outstanding interval is defined unti… 102 …"BriefDescription": "Non-modified cache lines that are silently dropped by L2 cache when triggered… 108 …y an L2 cache fill. These lines are typically in Shared or Exclusive state. A non-threaded event.", 216 "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.", 228 "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that miss L2 cache.", 270 …"BriefDescription": "Core-originated cacheable requests that missed L3 (Except hardware prefetche… 276 … "Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Reques… 282 …"BriefDescription": "Core-originated cacheable requests that refer to L3 (Except hardware prefetch… 288 …n": "Counts core-originated cacheable requests to the L3 cache (Longest Latency cache). Requests i… [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/sapphirerapids/
H A D	other.json	44 …t, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are con… 55 … on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.", 88 …t, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are con… 121 … on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.", 154 …t, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are con… 165 … on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.", 231 …t, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are con… 242 …er or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts DRAM accesses that are controlled by … 253 …her or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts PMM accesses that are controlled by … 308 … on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.",
H A D	cache.json	9 …opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.", 65 …-demand loads and gets hit at least once by demand. The valid outstanding interval is defined unti… 103 …"BriefDescription": "Non-modified cache lines that are silently dropped by L2 cache when triggered… 109 …y an L2 cache fill. These lines are typically in Shared or Exclusive state. A non-threaded event.", 125 …"BriefDescription": "Read requests with true-miss in L2 cache.[This event is alias to L2_RQSTS.MIS… 131 …ublicDescription": "Counts read requests of any type with true-miss in the L2 cache. True-miss exc… 235 …"BriefDescription": "Read requests with true-miss in L2 cache.[This event is alias to L2_REQUEST.M… 241 …ublicDescription": "Counts read requests of any type with true-miss in the L2 cache. True-miss exc… 263 "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.", 274 "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that miss L2 cache.", [all …]
/freebsd/sys/contrib/device-tree/Bindings/remoteproc/
H A D	ti,k3-r5f-rproc.yaml	`1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/remoteproc/ti,k3-r5 [all...]`
H A D	xlnx,zynqmp-r5fss.yaml	1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/remoteproc/xlnx,zynqmp-r5fss.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Ben Levinsky <ben.levinsky@amd.com> 11 - Tanmay Shah <tanmay.shah@amd.com> 14 The Xilinx platforms include a pair of Cortex-R5F processors (RPU) for 15 real-time processing based on the Cortex-R5F processor core from ARM. 16 The Cortex-R5F processor implements the Arm v7-R architecture and includes a 17 floating-point unit that implements the Arm VFPv3 instruction set. [all …]
/freebsd/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a55/
H A D	cache.json	105 …her they allocate. If either the core is configured without a per-core L2 or the cluster is config… 108 …her they allocate. If either the core is configured without a per-core L2 or the cluster is config… 111 …-core L2 cache: This event does not count. +//0 If the core is configured without a per-core L2 ca… 114 …-core L2 cache: This event does not count. +//0 If the core is configured without a per-core L2 ca… 117 …This event counts any linefills from the prefetcher which cause an allocation into the L1 D-cache", 120 … This event counts any linefills from the prefetcher which cause an allocation into the L1 D-cache" 123 …on": "Level 2 cache write streaming mode. This event counts for each cycle where the core is in wr… 126 …on": "Level 2 cache write streaming mode. This event counts for each cycle where the core is in wr… 129 …"Level 1 data cache entering write streaming mode.This event counts for each entry into write-stre… 132 …"Level 1 data cache entering write streaming mode.This event counts for each entry into write-stre… [all …]
/freebsd/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a510/
H A D	cache.json	102 …-complex L2 cache, this event does not count. If the complex is configured without a per-complex L… 105 …-complex L2 cache, this event does not count. If the complex is configured without a per-complex L… 114 …ription": "L2 cache write streaming mode. This event counts for each cycle where the core is in wr… 117 …ription": "L2 cache write streaming mode. This event counts for each cycle where the core is in wr… 120 …n": "L1 data cache entering write streaming mode. This event counts for each entry into write stre… 123 …n": "L1 data cache entering write streaming mode. This event counts for each entry into write stre… 126 …on": "L1 data cache write streaming mode. This event counts for each cycle where the core is in wr… 129 …on": "L1 data cache write streaming mode. This event counts for each cycle where the core is in wr… 132 …ription": "L3 cache write streaming mode. This event counts for each cycle where the core is in wr… 135 …ription": "L3 cache write streaming mode. This event counts for each cycle where the core is in wr… [all …]
/freebsd/usr.bin/mkuzip/
H A D	mkuzip.8	`1 .\"- 2 .\" Copyright (c) 2004-2016 Maxim Sobolev <sobomax@FreeBSD.org> 48 class will be able to decompress the resulting image at run-time. 56 .Bl -enum 60 image is split into clusters; each cluster is compressed. 69 .Bl -tag -width indent 96 For any given algorithm, a lesser number selects a faster compression mode. 97 A greater number selects a slower compression mode. 105 .Va 0-9 . 114 .Va 1-9 . [all …]`
/freebsd/share/man/man4/
H A D	ctl.4	`2 .\" Copyright (c) 2015-2017 Alexander Motin <mav@FreeBSD.org> 35 .Bd -ragged -offset indent 42 .Bd -literal -offset indent 51 .Bl -bullet -compact 53 Disk, CD-ROM and processor device emulation 70 Extensive VPD/mode/log pages support 76 All I/O handled in-kernel, no userland context switch overhead 83 .Bl -tag -width cfumass 85 Provides access for local system via virtual initiator mode 89 Provides access for remote systems via target mode [all …]`
H A D	rl.4	`15 .\" 4. Neither the name of the author nor the names of any co-contributors 41 .Bd -ragged -offset indent 49 .Bd -literal -offset indent 60 descriptor-based data transfer mechanism. 85 .Bl -tag -width xxxxxxxxxxxxxxxxxxxx 92 the autoselected mode by adding media options to the 100 .Ar full-duplex 102 .Ar half-duplex 109 .Ar full-duplex 111 .Ar half-duplex [all …]`
/freebsd/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a65/
H A D	cache.json	111 … prefetch. Counts any linefills from the prefetcher which cause an allocation into the L1 D-cache", 114 …o prefetch. Counts any linefills from the prefetcher which cause an allocation into the L1 D-cache" 117 …-core L2 cache: This event does not count. +//0 If the core is configured without a per-core L2 ca… 120 …-core L2 cache: This event does not count. +//0 If the core is configured without a per-core L2 ca… 123 …her they allocate. If either the core is configured without a per-core L2 or the cluster is config… 126 …her they allocate. If either the core is configured without a per-core L2 or the cluster is config… 129 "PublicDescription": "L1D entering write stream mode", 132 "BriefDescription": "L1D entering write stream mode" 135 "PublicDescription": "L1D is in write stream mode", 138 "BriefDescription": "L1D is in write stream mode" [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/knightslanding/
H A D	cache.json	3 …the L2Q because of any L2 queue reject condition. There is no concept of at-ret here. It might in… 35 … and L1 evictions (automatically exlcudes L2HWP, UC, WC) that were rejected - Multiple repeated re… 42 "BriefDescription": "Counts all the load micro-ops retired", 46 "PublicDescription": "This event counts the number of load micro-ops retired.", 51 "BriefDescription": "Counts all the store micro-ops retired", 55 "PublicDescription": "This event counts the number of store micro-ops retired.", 70 "BriefDescription": "Counts the number of load micro-ops retired that miss in L1 D cache", 74 …"PublicDescription": "This event counts the number of load micro-ops retired that miss in L1 Data … 79 "BriefDescription": "Counts the number of load micro-ops retired that hit in the L2", 89 "BriefDescription": "Counts the number of load micro-ops retired that miss in the L2", [all …]
/freebsd/sys/contrib/alpine-hal/
H A D	al_hal_nb_regs.h	1 /- 10 found at http://www.gnu.org/licenses/gpl-2.0.html 66 / [0xc] Force init reset per DECEI mode. / 101 / [0x6c] Read-only that reflects CPU Cluster Local GIC base high address / 103 / [0x70] Read-only that reflects CPU Cluster Local GIC base low address / 105 / [0x74] Read-only that reflects the device's IOGIC base high address. / 107 / [0x78] Read-only that reflects IOGIC base low address / 452 Connect to Processor Cluster SYSBARDISABLE. / 455 Connect to Processor Cluster BROADCASTINNER. / 458 Connect to Processor Cluster BROADCASTCACHEMAIN / [all …]
/freebsd/usr.bin/hesinfo/
H A D	hesinfo.1	`44 .Bl -tag -width indent 48 Prints the fully\-qualified string passed to the nameserver. 58 .Bl -tag -width indent 60 the 8\-character\-or\-less string used to identify users or classes 74 .It Aq Ar file\-system\-name 77 .Ao Ar "rvd\-server" Ac : Ns Aq Ar pack 81 .Ao Ar "nfs\-server" Ac : Ns Aq Ar partition 86 .It Aq Ar workstation\-name 87 the machine name of an Athena workstation (e.g.\& E40\-343\-3). 88 .It Aq Ar service\-name [all …]`
/freebsd/sys/contrib/device-tree/Bindings/opp/
H A D	opp-v2.yaml	`1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/opp/opp-v2.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Viresh Kumar <viresh.kumar@linaro.org> 13 - $ref: opp-v2-base.yaml# 17 const: operating-points-v2 22 - \| 24 * Example 1: Single cluster Dual-core ARM cortex A9, switch DVFS states 28 #address-cells = <1>; [all …]`
H A D	opp.txt	`2 ---------------------------------------------------- 4 Devices work at voltage-current-frequency combinations and some implementations 13 Binding 1: operating-points 16 This binding only supports voltage-frequency pairs. 19 - operating-points: An array of 2-tuples items, and each item consists 20 of frequency and voltage like <freq-kHz vol-uV>. 27 compatible = "arm,cortex-a9"; 29 next-level-cache = <&L2>; 30 operating-points = < 39 Binding 2: operating-points-v2 [all …]`
/freebsd/sys/contrib/device-tree/Bindings/cpu/
H A D	idle-states.yaml	1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/cpu/idle-states.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> 11 - Anup Patel <anup@brainfault.org> 15 1 - Introduction 18 ARM and RISC-V systems contain HW capable of managing power consumption 19 dynamically, where cores can be put in different low-power states (ranging 22 run-time, can be specified through device tree bindings representing the [all …]
/freebsd/usr.sbin/fstyp/
H A D	hammer2_disk.h	1 /- 2 Copyright (c) 2011-2018 The DragonFly Project. All rights reserved. 68 * The structures below represent the on-disk media structures for the HAMMER2 69 * filesystem. Note that all fields for on-disk structures are naturally 70 * aligned. The host endian format is typically used - compatibility is 77 * references utilize 64-bit byte offsets. 94 * A full indirect block use supports 512 x 128-byte blockrefs in a 64KB 98 * A maximally sized file (2^64-1 bytes) requires ~6 indirect block levels 114 * MINALLOCSIZE - The minimum allocation size. This can be smaller 120 * MINIOSIZE - Th 989 uint32_t mode; /* 0054 unix modes (typ low 16 bits) */ global() member [all...]
/freebsd/contrib/ntp/html/scripts/
H A D	special.txt	`4 <li class='inline'><a href='autokey.html'>Autokey Public-Key Authentication</a></li>\ 5 <li class='inline'><a href='orphan.html'>Orphan Mode</a></li>\ 7 <li class='inline'><a href='huffpuff.html'>Huff-n'-Puff Filter</a></li>\ 10 <li class='inline'><a href='cluster.html'>Clock Cluster Algorithm</a></li>\`
/freebsd/sys/contrib/device-tree/Bindings/arm/
H A D	psci.yaml	`1 # SPDX-License-Identifier: GPL-2.0 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> 15 processors") can be used by Linux to initiate various CPU-centric power 25 r0 => 32-bi [all...]`
H A D	idle-states.yaml	`1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/arm/idle-states.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> 14 1 - Introduction 18 where cores can be put in different low-power states (ranging from simple wfi 20 range of dynamic idle states that a processor can enter at run-time, can be 27 - Running 28 - Idle_standby [all …]`
/freebsd/sys/fs/ext2fs/
H A D	ext2_alloc.c	`1 /- 7 /- 8 * SPDX-License-Identifier: BSD-3-Clause 109 fs = ip->i_e2fs; in ext2_alloc() 110 ump = ip->i_ump; in ext2_alloc() 113 if ((u_int)size > fs->e2fs_bsize \|\| blkoff(fs, size) != 0) { in ext2_alloc() 114 vn_printf(ip->i_devvp, "bsize = %lu, size = %d, fs = %s\n", in ext2_alloc() 115 (long unsigned int)fs->e2fs_bsize, size, fs->e2fs_fsmnt); in ext2_alloc() 121 if (size == fs->e2fs_bsize && fs->e2fs_fbcount == 0) in ext2_alloc() 123 if (cred->cr_uid != 0 && in ext2_alloc() [all …]`
/freebsd/sys/amd64/vmm/io/
H A D	vlapic.c	1 /- 2 SPDX-License-Identifier: BSD-2-Clause 62 #define x2apic(vlapic) (((vlapic)->msr_apicbase & APICBASE_X2APIC) ? 1 : 0) 65 * The 'vlapic->timer_mtx' is used to provide mutual exclusion between the 67 * - timer_freq_bt, timer_period_bt, timer_fire_bt 68 * - timer LVT register 70 #define VLAPIC_TIMER_LOCK(vlapic) mtx_lock_spin(&((vlapic)->timer_mtx)) 71 #define VLAPIC_TIMER_UNLOCK(vlapic) mtx_unlock_spin(&((vlapic)->timer_mtx)) 72 #define VLAPIC_TIMER_LOCKED(vlapic) mtx_owned(&((vlapic)->timer_mtx)) 76 * - arbitrary but chosen to be in the ballpark of contemporary hardware. [all …]

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