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/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Dmrvl,intc.txt4 - compatible : Should be
5 "mrvl,mmp-intc" on Marvel MMP,
6 "mrvl,mmp2-intc" along with "mrvl,mmp2-mux-intc" on MMP2 or
7 "marvell,mmp3-intc" with "mrvl,mmp2-mux-intc" on MMP3
8 - reg : Address and length of the register set of the interrupt controller.
10 of the whole interrupt controller. The "marvell,mmp3-intc" controller
12 controller is mux-intc, address and length means one register. Since
13 address of mux-intc is in the range of intc. mux-intc is secondary
15 - reg-names : Name of the register set of the interrupt controller. It's
16 only required in mux-intc interrupt controller.
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H A Dmrvl,intc.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/mrvl,intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Gregory Clement <gregory.clement@bootlin.com>
14 - if:
19 const: marvell,orion-intc
22 - mrvl,intc-nr-irqs
23 - if:
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/freebsd/sys/contrib/device-tree/src/arm/marvell/
H A Dmmp2.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <dt-bindings/clock/marvell,mmp2.h>
8 #include <dt-bindings/power/marvell,mmp2.h>
9 #include <dt-bindings/clock/marvell,mmp2-audio.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
25 #address-cells = <1>;
26 #size-cells = <1>;
27 compatible = "simple-bus";
28 interrupt-parent = <&intc>;
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/freebsd/sys/dev/iwm/
H A Dif_iwmreg.h10 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
31 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
35 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
73 * BEGIN iwl-csr.h
81 * low power states due to driver-invoked device resets
82 * (e.g. IWM_CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes.
95 #define IWM_CSR_INT_COALESCING (0x004) /* accum ints, 32-usec units */
109 * 31-16: Reserved
110 * 15-4: Type of device: see IWM_CSR_HW_REV_TYPE_xxx definitions
111 * 3-2: Revision step: 0 = A, 1 = B, 2 = C, 3 = D
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