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/linux/drivers/video/backlight/
H A Dpandora_bl.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Pandora uses TWL4030 PWM0 -> TPS61161 combo for control backlight.
32 #define MAX_USER_VALUE (MAX_VALUE - MIN_VALUE)
41 int brightness = bl->props.brightness; in pandora_backlight_update_status()
45 if (bl->props.power != BACKLIGHT_POWER_ON) in pandora_backlight_update_status()
47 if (bl->props.state & BL_CORE_FBBLANK) in pandora_backlight_update_status()
49 if (bl->props.state & BL_CORE_SUSPENDED) in pandora_backlight_update_status()
56 if (priv->old_state == PANDORABL_WAS_OFF) in pandora_backlight_update_status()
59 /* first disable PWM0 output, then clock */ in pandora_backlight_update_status()
69 if (priv->old_state == PANDORABL_WAS_OFF) { in pandora_backlight_update_status()
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H A Dcorgi_lcd.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (c) 2004-2006 Richard Purdie
43 #define POWER1_GVSS_ON 0x02 /* GVSS(-8V) Power Supply ON */
44 #define POWER1_VDD_ON 0x04 /* VDD(8V),SVSS(-4V) Power Supply ON */
47 #define POWER1_GVSS_OFF 0x00 /* GVSS(-8V) Power Supply OFF */
48 #define POWER1_VDD_OFF 0x00 /* VDD(8V),SVSS(-4V) Power Supply OFF */
50 #define POWER0_COM_DCLK 0x01 /* COM Voltage DC Bias DAC Serial Data Clock */
176 .tx_buf = lcd->buf, in corgi_ssp_lcdtg_send()
179 lcd->buf[0] = ((adrs & 0x07) << 5) | (data & 0x1f); in corgi_ssp_lcdtg_send()
183 return spi_sync(lcd->spi_dev, &msg); in corgi_ssp_lcdtg_send()
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/linux/Documentation/devicetree/bindings/arm/altera/
H A Dsocfpga-clk-manager.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/arm/altera/socfpga-clk-manager.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Altera SOCFPGA Clock Manager
10 - Dinh Nguyen <dinguyen@kernel.org>
13 This binding describes the Altera SOCFGPA Clock Manager and its associated
14 tree of clocks, pll's, and clock gates for the Cyclone5, Arria5 and Arria10
20 - const: altr,clk-mgr
30 "#address-cells":
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/linux/sound/soc/generic/
H A Dsimple-card-utils.c1 // SPDX-License-Identifier: GPL-2.0
3 // simple-card-utils.c
7 #include <dt-bindings/sound/audio-graph.h>
28 int val = -EINVAL; in simple_util_get_sample_fmt()
42 if (!strcmp(data->convert_sample_format, in simple_util_get_sample_fmt()
79 snprintf(prop, sizeof(prop), "%s%s", prefix, "convert-rate"); in simple_util_parse_convert()
80 of_property_read_u32(np, prop, &data->convert_rate); in simple_util_parse_convert()
83 snprintf(prop, sizeof(prop), "%s%s", prefix, "convert-channels"); in simple_util_parse_convert()
84 of_property_read_u32(np, prop, &data->convert_channels); in simple_util_parse_convert()
87 snprintf(prop, sizeof(prop), "%s%s", prefix, "convert-sample-format"); in simple_util_parse_convert()
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/linux/Documentation/devicetree/bindings/spi/
H A Dfsl,dspi-peripheral-props.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/fsl,dspi-peripheral-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Peripheral-specific properties for Freescale DSPI controller
10 - Vladimir Oltean <olteanv@gmail.com>
13 See spi-peripheral-props.yaml for more info.
16 fsl,spi-cs-sck-delay:
20 clock signal, at the start of a transfer.
23 fsl,spi-sck-cs-delay:
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H A Dspi-peripheral-props.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-peripheral-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Peripheral-specific properties for a SPI bus.
11 be common properties like spi-max-frequency, spi-cs-high, etc. or they could
12 be controller specific like delay in clock or data lines, etc. These
14 per-peripheral and there can be multiple peripherals attached to a
20 - Mark Brown <broonie@kernel.org>
28 - minimum: 0
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H A Dcdns,qspi-nor-peripheral-props.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/cdns,qspi-nor-peripheral-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Peripheral-specific properties for the Cadence QSPI controller.
10 See spi-peripheral-props.yaml for more info.
13 - Vaishnav Achath <vaishnav.a@ti.com>
16 # cdns,qspi-nor.yaml
17 cdns,read-delay:
20 Delay for read capture logic, in clock cycles.
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H A Dnvidia,tegra210-quad-peripheral-props.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/nvidia,tegra210-quad-peripheral-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jonathan Hunter <jonathanh@nvidia.com>
14 nvidia,tx-clk-tap-delay:
16 Delays the clock going out to device with this tap value.
23 nvidia,rx-clk-tap-delay:
25 Delays the clock coming in from the device with this tap value.
/linux/drivers/usb/dwc3/
H A Ddwc3-xilinx.c1 // SPDX-License-Identifier: GPL-2.0
3 * dwc3-xilinx.c - Xilinx DWC3 controller specific glue driver
15 #include <linux/dma-mapping.h>
22 #include <linux/firmware/xlnx-zynqmp.h>
62 reg = readl(priv_data->regs + XLNX_USB_PHY_RST_EN); in dwc3_xlnx_mask_phy_rst()
69 writel(reg, priv_data->regs + XLNX_USB_PHY_RST_EN); in dwc3_xlnx_mask_phy_rst()
74 struct device *dev = priv_data->dev; in dwc3_xlnx_set_coherency()
82 if (of_dma_is_coherent(dev->of_node) || device_iommu_mapped(dev)) { in dwc3_xlnx_set_coherency()
83 reg = readl(priv_data->regs + coherency_offset); in dwc3_xlnx_set_coherency()
85 writel(reg, priv_data->regs + coherency_offset); in dwc3_xlnx_set_coherency()
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/linux/sound/soc/intel/boards/
H A Dbytcr_rt5651.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * bytcr_rt5651.c - ASoc Machine driver for Intel Byt CR platform
29 #include <sound/soc-acpi.h>
31 #include "../atom/sst-atom-controls.h"
32 #include "../common/soc-intel-quirk
530 struct property_entry props[MAX_NO_PROPS] = {}; byt_rt5651_add_codec_device_props() local
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H A Dbytcr_rt5640.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * byt_cr_dpcm_rt5640.c - ASoc Machine driver for Intel Byt CR platform
30 #include <sound/soc-acpi.h>
31 #include <dt-bindings/sound/rt5640.h>
33 #include "../atom/sst-atom-controls.h"
34 #include "../common/soc-inte
1211 struct property_entry props[MAX_NO_PROPS] = {}; byt_rt5640_add_codec_device_props() local
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/linux/drivers/gpu/drm/panel/
H A Dpanel-jdi-lt070me05000.c1 // SPDX-License-Identifier: GPL-2.0-only
50 struct mipi_dsi_device *dsi = jdi->dsi; in jdi_panel_init()
51 struct device *dev = &jdi->dsi->dev; in jdi_panel_init()
54 dsi->mode_flags |= MIPI_DSI_MODE_LPM; in jdi_panel_init()
68 ret = mipi_dsi_dcs_set_column_address(dsi, 0, jdi->mode->hdisplay - 1); in jdi_panel_init()
74 ret = mipi_dsi_dcs_set_page_address(dsi, 0, jdi->mode->vdisplay - 1); in jdi_panel_init()
140 struct mipi_dsi_device *dsi = jdi->dsi; in jdi_panel_on()
141 struct device *dev = &jdi->dsi->dev; in jdi_panel_on()
144 dsi->mode_flags |= MIPI_DSI_MODE_LPM; in jdi_panel_on()
155 struct mipi_dsi_device *dsi = jdi->dsi; in jdi_panel_off()
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/linux/drivers/gpu/drm/i915/
H A Di915_perf.c2 * Copyright © 2015-2016 Intel Corporation
44 * without special privileges. Access to system-wide metrics requires root
58 * might sample sets of tightly-coupled counters, depending on the
70 * interleaved with event-type specific members.
76 * would be acceptable to expose them to unprivileged applications - to hide
96 * side-band OA data captured via MI_REPORT_PERF_COUNT commands; we're
102 * For posterity, in case we might re-visit trying to adapt core perf to be
106 * - The perf based OA PMU driver broke some significant design assumptions:
110 * implications, the need to fake cpu-related data (such as user/kernel
112 * as a way to forward device-specific status records.
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/linux/Documentation/devicetree/bindings/rtc/
H A Dnxp,pcf85063.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP PCF85063 Real Time Clock
10 - Alexander Stein <alexander.stein@ew.tq-group.com>
15 - microcrystal,rv8063
16 - microcrystal,rv8263
17 - nxp,pcf85063
18 - nxp,pcf85063a
19 - nxp,pcf85063tp
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H A Dnxp,pcf2123.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP PCF2123 SPI Real Time Clock
10 - Javier Carrasco <javier.carrasco.cruz@gmail.com>
13 - $ref: /schemas/spi/spi-peripheral-props.yaml#
14 - $ref: rtc.yaml#
19 - nxp,pcf2123
28 - compatible
29 - reg
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/linux/Documentation/devicetree/bindings/serial/
H A Dmaxim,max310x.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Maxim MAX310X Advanced Universal Asynchronous Receiver-Transmitter (UART)
10 - Hugo Villeneuve <hvilleneuve@dimonoff.com>
15 - maxim,max3107
16 - maxim,max3108
17 - maxim,max3109
18 - maxim,max14830
29 clock-names:
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/linux/Documentation/devicetree/bindings/gpio/
H A Dfairchild,74hc595.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic 8-bit shift register
11 have a rising-edge triggered latch clock (or storage register clock) pin,
12 which behaves like an active-low chip select.
15 the 74HC595 sees as a rising edge on the latch clock that results in a
19 shift clock ____| |_| |_..._| |_| |_________
21 latch clock * trigger
27 - Maxime Ripard <mripard@kernel.org>
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/linux/Documentation/devicetree/bindings/clock/
H A Dzynq-7000.txt1 Device Tree Clock bindings for the Zynq 7000 EPP
6 See clock_bindings.txt for more information on the generic clock bindings.
9 == Clock Controller ==
10 The clock controller is a logical abstraction of Zynq's clock tree. It reads
11 required input clock frequencies from the devicetree and acts as clock provider
12 for all clock consumers of PS clocks.
15 - #clock-cells : Must be 1
16 - compatible : "xlnx,ps7-clkc"
17 - reg : SLCR offset and size taken via syscon < 0x100 0x100 >
18 - ps-clk-frequency : Frequency of the oscillator providing ps_clk in HZ
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/linux/Documentation/devicetree/bindings/iio/frequency/
H A Dadi,adf4377.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Antoniu Miclaus <antoniu.miclaus@analog.com>
11 - Dragos Bogdan <dragos.bogdan@analog.com>
14 The ADF4377 is a high performance, ultralow jitter, dual output integer-N
16 ideally suited for data converter and mixed signal front end (MxFE) clock
25 - adi,adf4377
26 - adi,adf4378
31 spi-max-frequency:
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H A Dadi,adrf6780.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Antoniu Miclaus <antoniu.miclaus@analog.com>
21 - adi,adrf6780
26 spi-max-frequency:
31 Definition of the external clock.
34 clock-names:
36 - const: lo_in
38 clock-output-names:
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/linux/Documentation/devicetree/bindings/sound/
H A Drealtek,rt5514.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Animesh Agarwal <animeshagarwal28@gmail.com>
24 - $ref: /schemas/spi/spi-peripheral-props.yaml#
25 - $ref: dai-common.yaml#
36 - description: Master clock to the CODEC
38 clock-names:
40 - const: mclk
46 realtek,dmic-init-delay-ms:
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/linux/Documentation/devicetree/bindings/net/wireless/
H A Dti,wlcore.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tony Lindgren <tony@atomide.com>
14 Note that the *-clock-frequency properties assume internal clocks. In case
15 of external clocks, new bindings (for parsing the clock nodes) have to be
21 - ti,wl1271
22 - ti,wl1273
23 - ti,wl1281
24 - ti,wl1283
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/linux/Documentation/devicetree/bindings/iio/adc/
H A Dadi,ad4080.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Analog Devices AD4080 20-Bit, 40 MSPS, Differential SAR ADC
11 - Antoniu Miclaus <antoniu.miclaus@analog.com>
14 The AD4080 is a high speed, low noise, low distortion, 20-bit, Easy Drive,
15 successive approximation register (SAR) analog-to-digital converter (ADC).
16 Maintaining high performance (signal-to-noise and distortion (SINAD) ratio
21 https://www.analog.com/media/en/technical-documentation/data-sheets/ad4080.pdf
23 $ref: /schemas/spi/spi-peripheral-props.yaml#
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/linux/Documentation/devicetree/bindings/net/
H A Dmaxim,ds26522.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
15 - const: maxim,ds26522
21 - compatible
22 - reg
25 - $ref: /schemas/spi/spi-peripheral-props.yaml
30 - |
32 #address-cells = <1>;
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/linux/drivers/gpio/
H A Dgpio-aspeed.c1 // SPDX-License-Identifier: GPL-2.0-or-later
34 /* Non-constant mask variant of FIELD_GET() and FIELD_PREP() */
35 #define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1))
36 #define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask))
63 const struct aspeed_bank_props *props; member
262 return gpio->base + bank->val_regs + GPIO_VAL_VALUE; in aspeed_gpio_g4_bank_reg()
264 return gpio->base + bank->rdata_reg; in aspeed_gpio_g4_bank_reg()
266 return gpio->base + bank->val_regs + GPIO_VAL_DIR; in aspeed_gpio_g4_bank_reg()
268 return gpio->base + bank->irq_regs + GPIO_IRQ_ENABLE; in aspeed_gpio_g4_bank_reg()
270 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE0; in aspeed_gpio_g4_bank_reg()
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