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/linux/drivers/clk/sunxi-ng/
H A Dccu_phase.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 #include <linux/clk-provider.h>
15 struct ccu_phase *phase = hw_to_ccu_phase(hw); in ccu_phase_get_phase() local
22 reg = readl(phase->common.base + phase->common.reg); in ccu_phase_get_phase()
23 delay = (reg >> phase->shift); in ccu_phase_get_phase()
24 delay &= (1 << phase->width) - 1; in ccu_phase_get_phase()
29 /* Get our parent clock, it's the one that can adjust its rate */ in ccu_phase_get_phase()
32 return -EINVAL; in ccu_phase_get_phase()
37 return -EINVAL; in ccu_phase_get_phase()
[all …]
/linux/drivers/clk/sunxi/
H A Dclk-mod0.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/clk-provider.h>
15 #include "clk-factors.h"
18 * sun4i_a10_get_mod0_factors() - calculates m, n factors for MOD0-style clocks
29 if (req->rate > req->parent_rate) in sun4i_a10_get_mod0_factors()
30 req->rate = req->parent_rate; in sun4i_a10_get_mod0_factors()
32 div = DIV_ROUND_UP(req->parent_rate, req->rate); in sun4i_a10_get_mod0_factors()
45 req->rate = (req->parent_rate >> calcp) / calcm; in sun4i_a10_get_mod0_factors()
46 req->m = calcm - 1; in sun4i_a10_get_mod0_factors()
47 req->p = calcp; in sun4i_a10_get_mod0_factors()
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/linux/drivers/media/i2c/
H A Dsaa711x_regs.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * saa711x - Philips SAA711x video decoder register specifications
10 /* Video Decoder - Frontend part */
16 /* Video Decoder - Decoder part */
56 /* Audio clock generator part */
112 /* Horizontal phase scaling */
159 /* Horizontal phase scaling */
196 /* SAA7113 bit-masks */
230 /* Video Decoder - Frontend part: R_01_INC_DELAY to R_05_INPUT_CNTL_4 */
242 /* Video Decoder - Decoder part: R_06_H_SYNC_START to R_1F_STATUS_BYTE_2_VD_DEC */
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/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn21/
H A Ddcn21_dccg.c35 (dccg_dcn->regs->reg)
39 dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name
42 dccg_dcn->base.ctx
44 dccg->ctx->logger
50 if (dccg->ref_dppclk) { in dccg21_update_dpp_dto()
51 int ref_dppclk = dccg->ref_dppclk; in dccg21_update_dpp_dto()
53 int phase; in dccg21_update_dpp_dto() local
57 * program DPP DTO phase and modulo as below in dccg21_update_dpp_dto()
58 * phase = ceiling(dpp_pipe_clk_mhz / 10) in dccg21_update_dpp_dto()
64 * ceiling phase and truncate modulo guarentees the divided in dccg21_update_dpp_dto()
[all …]
/linux/Documentation/devicetree/bindings/watchdog/
H A Drealtek,otto-wdt.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/watchdog/realtek,otto-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sander Vanheule <sander@svanheule.net>
14 prescaled clock ticks, which is ca. 43s with a bus clock of 200MHz. The
15 minimum duration of each phase is one tick. Each phase can trigger an
16 interrupt, although the phase 2 interrupt will occur with the system reset.
17 - Phase 1: During this phase, the WDT can be pinged to reset the timeout.
18 - Phase 2: Starts after phase 1 has timed out, and only serves to give the
[all …]
H A Dstarfive,jh7100-wdt.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/starfive,jh7100-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Xingyu Wu <xingyu.wu@starfivetech.com>
11 - Samin Guo <samin.guo@starfivetech.com>
15 has only one timeout phase and reboots. And JH7110 watchdog has two
16 timeout phases. At the first phase, the signal of watchdog interrupt
25 - enum:
26 - starfive,jh7100-wdt
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/linux/sound/soc/pxa/
H A Dmmp-sspa.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * linux/sound/soc/pxa/mmp-sspa.h
24 #define SSPA_CTL_XPH (1 << 31) /* Read Phase */
28 #define SSPA_CTL_XFRLEN2(x) ((x) << 24) /* Transmit Frame Length in Phase 2 */
30 #define SSPA_CTL_XWDLEN2(x) ((x) << 21) /* Transmit Word Length in Phase 2 */
35 #define SSPA_CTL_XFRLEN1(x) ((x) << 8) /* Transmit Frame Length in Phase 1 */
37 #define SSPA_CTL_XWDLEN1(x) ((x) << 5) /* Transmit Word Length in Phase 1 */
51 #define SSPA_SP_CLKP (1 << 17) /* CLKP Polarity Clock Edge Select */
52 #define SSPA_SP_FSP (1 << 16) /* FSP Polarity Clock Edge Select */
55 #define SSPA_SP_S_EN (1 << 0) /* Serial Clock Domain Enable */
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/linux/Documentation/devicetree/bindings/mmc/
H A Dsynopsys-dw-mshc.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/synopsys-dw-mshc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
16 - altr,socfpga-dw-mshc
17 - img,pistachio-dw-mshc
18 - snps,dw-mshc
31 bus interface unit clock and the card interface unit clock.
33 clock-names:
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H A Dhisilicon,hi3798cv200-dw-mshc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mmc/hisilicon,hi3798cv200-dw-mshc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Yang Xiwen <forbidden405@outlook.com>
15 - hisilicon,hi3798cv200-dw-mshc
16 - hisilicon,hi3798mv200-dw-mshc
26 - description: bus interface unit clock
27 - description: card interface unit clock
28 - description: card input sample phase clock
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Dlantiq,pef2256.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Herve Codina <herve.codina@bootlin.com>
20 - const: lantiq,pef2256
27 - description: Master Clock
28 - description: System Clock Receive
29 - description: System Clock Transmit
31 clock-names:
33 - const: mclk
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/linux/drivers/clk/hisilicon/
H A Dclk-hisi-phase.c1 // SPDX-License-Identifier: GPL-2.0
5 * Simple HiSilicon phase clock implementation.
30 static int hisi_phase_regval_to_degrees(struct clk_hisi_phase *phase, in hisi_phase_regval_to_degrees() argument
35 for (i = 0; i < phase->phase_num; i++) in hisi_phase_regval_to_degrees()
36 if (phase->phase_regvals[i] == regval) in hisi_phase_regval_to_degrees()
37 return phase->phase_degrees[i]; in hisi_phase_regval_to_degrees()
39 return -EINVAL; in hisi_phase_regval_to_degrees()
44 struct clk_hisi_phase *phase = to_clk_hisi_phase(hw); in hisi_clk_get_phase() local
47 regval = readl(phase->reg); in hisi_clk_get_phase()
48 regval = (regval & phase->mask) >> phase->shift; in hisi_clk_get_phase()
[all …]
/linux/drivers/net/ethernet/intel/ice/
H A Dice_dpll.h1 /* SPDX-License-Identifier: GPL-2.0 */
12 * enum ice_dpll_pin_sw - enumerate ice software pin indices:
23 /** ice_dpll_pin - store info about pins
33 * @phase_adjust: current phase adjust value
34 * @phase_offset: monitored phase offset value
58 /** ice_dpll - store info required for DPLL control
66 * @phase_offset: phase offset of active pin vs dpll signal
67 * @prev_phase_offset: previous phase offset of active pin vs dpll signal
71 * @phase_offset_monitor_period: period for phase offset monitor read frequency
96 /** ice_dplls - store info required for CCU (clock controlling unit)
[all …]
/linux/Documentation/devicetree/bindings/iio/frequency/
H A Dadi,adf4350.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michael Hennerich <michael.hennerich@analog.com>
15 - adi,adf4350
16 - adi,adf4351
21 spi-max-frequency:
26 description: Clock to provide CLKIN reference clock signal.
28 clock-names:
31 '#clock-cells':
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/linux/drivers/net/can/dev/
H A Dbittiming.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (C) 2005 Marc Kleine-Budde, Pengutronix
4 * Copyright (C) 2008-2009 Wolfgang Grandegger <wg@grandegger.com>
11 if (bt->sjw) in can_sjw_set_default()
15 bt->sjw = max(1U, min(bt->phase_seg1, bt->phase_seg2 / 2)); in can_sjw_set_default()
21 if (bt->sjw > btc->sjw_max) { in can_sjw_check()
23 bt->sjw, btc->sjw_max); in can_sjw_check()
24 return -EINVAL; in can_sjw_check()
27 if (bt->sjw > bt->phase_seg1) { in can_sjw_check()
29 "sjw: %u greater than phase-seg1: %u", in can_sjw_check()
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/linux/Documentation/devicetree/bindings/iio/dac/
H A Dadi,ad5755.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Analog Devices AD5755 Multi-Channel DAC
10 - Sean Nyekjaer <sean.nyekjaer@prevas.dk>
15 - adi,ad5755
16 - adi,ad5755-1
17 - adi,ad5757
18 - adi,ad5735
19 - adi,ad5737
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/linux/drivers/mmc/host/
H A Dmmci_stm32_sdmmc.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
8 #include <linux/dma-mapping.h>
71 int phase, bool sampler __maybe_unused);
84 struct sdmmc_idma *idma = host->dma_priv; in sdmmc_idma_validate_data()
85 struct device *dev = mmc_dev(host->mmc); in sdmmc_idma_validate_data()
93 idma->use_bounce_buffer = false; in sdmmc_idma_validate_data()
94 for_each_sg(data->sg, sg, data->sg_len - 1, i) { in sdmmc_idma_validate_data()
95 if (!IS_ALIGNED(sg->offset, sizeof(u32)) || in sdmmc_idma_validate_data()
96 !IS_ALIGNED(sg->length, in sdmmc_idma_validate_data()
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/linux/drivers/iio/frequency/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
5 # Clock Distribution device drivers
6 # Phase-Locked Loop (PLL) frequency synthesizers
12 menu "Clock Generator/Distribution"
15 tristate "Analog Devices AD9523 Low Jitter Clock Generator"
19 Clock Generator. The driver provides direct access via sysfs.
27 # Phase-Locked Loop (PLL) frequency synthesizers
30 menu "Phase-Locked Loop (PLL) frequency synthesizers"
100 Downconverter with integrated Fractional-N PLL and VCO.
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn35/
H A Ddcn35_dccg.c1 /* SPDX-License-Identifier: MIT */
34 (dccg_dcn->regs->reg)
38 dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name
41 dccg_dcn->base.ctx
44 dccg->ctx->logger
47 SYMCLK_FE_SYMCLK_A = 0, // Select functional clock from backend symclk A
65 PHYSYMCLK_PHYCLK = 0, // Select symclk as source of clock which is output to PHY through DCIO.
66 …PHYSYMCLK_PHYD18CLK, // Select phyd18clk as the source of clock which is output to PHY through DC…
67 …PHYSYMCLK_PHYD32CLK, // Select phyd32clk as the source of clock which is output to PHY through DC…
81 DPP_DCCG_DTO, // Functional clock selected is DTO tuned DPPCLK
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/linux/drivers/ptp/
H A Dptp_idt82p33.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * PTP hardware clock driver for the IDT 82P33XXX family of clocks.
46 * @brief Maximum absolute value for write phase offset in nanoseconds
50 /** @brief Phase offset resolution
52 * DPLL phase offset = 10^15 fs / ( System Clock * 2^13)
58 /* PTP Hardware Clock interface */
64 /* Workaround for TOD-to-output alignment issue */
/linux/drivers/staging/sm750fb/
H A Dddk750_mode.h1 /* SPDX-License-Identifier: GPL-2.0 */
32 /* Clock Phase. This clock phase only applies to Panel. */
36 int ddk750_set_mode_timing(struct mode_parameter *parm, enum clock_type clock);
/linux/include/uapi/linux/
H A Dptp_clock.h1 /* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
3 * PTP 1588 clock support - user space interface
83 * struct ptp_clock_time - represents a time value
87 * included for sub-nanosecond resolution, should the demand for
102 int pps; /* Whether the clock support
131 struct ptp_clock_time phase; global() member
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/linux/drivers/clk/
H A Dclk.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
6 * Standard functionality for the common clock API. See Documentation/driver-api/clk.rst
9 #include <linux/clk/clk-conf.h>
12 #include <linux/clk-provider.h>
92 int phase; member
123 if (!core->rpm_enabled) in clk_pm_runtime_get()
126 return pm_runtime_resume_and_get(core->dev); in clk_pm_runtime_get()
131 if (!core->rpm_enabled) in clk_pm_runtime_put()
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/linux/Documentation/scsi/
H A DChangeLog.sym53c8xx1 Sat May 12 12:00 2001 Gerard Roudier (groudier@club-internet.fr)
2 * version sym53c8xx-1.7.3c
3 - Ensure LEDC bit in GPCNTL is cleared when reading the NVRAM.
4 Fix sent by Stig Telfer <stig@api-networks.com>.
5 - Backport from SYM-2 the work-around that allows to support
7 - Check that we received at least 8 bytes of INQUIRY response
9 - Define scsi_set_pci_device() as nil for kernel < 2.4.4.
10 - + A couple of minor changes.
12 Sat Apr 7 19:30 2001 Gerard Roudier (groudier@club-internet.fr)
13 * version sym53c8xx-1.7.3b
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/linux/drivers/watchdog/
H A Drealtek_otto_wdt.c1 // SPDX-License-Identifier: GPL-2.0-only
10 * - Base prescale of (2 << 25), providing tick duration T_0: 168ms @ 200MHz
11 * - PRESCALE: logarithmic prescaler adding a factor of {1, 2, 4, 8}
12 * - Phase 1: Times out after (PHASE1 + 1) × PRESCALE × T_0
13 * Generates an interrupt, WDT cannot be stopped after phase 1
14 * - Phase 2: starts after phase 1, times out after (PHASE2 + 1) × PRESCALE × T_0
54 * One higher than the max values contained in PHASE{1,2}, since a value of 0
79 v = ioread32(ctrl->base + OTTO_WDT_REG_CTRL); in otto_wdt_start()
81 iowrite32(v, ctrl->base + OTTO_WDT_REG_CTRL); in otto_wdt_start()
91 v = ioread32(ctrl->base + OTTO_WDT_REG_CTRL); in otto_wdt_stop()
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/linux/Documentation/ABI/testing/
H A Dsysfs-timecard18 uses for clock adjustments.
24 IRIG adjustments from external IRIG-B signal
35 10Mhz signal is used as the 10Mhz reference clock
42 IRIG signal is sent to the IRIG-B module
57 10Mhz output is from the 10Mhz reference clock
58 PHC output PPS is from the PHC clock
59 MAC output PPS is from the Miniature Atomic Clock
62 IRIG output is from the PHC, in IRIG-B format
83 for internal disciplining of the atomic clock.
89 for internal disciplining of the atomic clock.
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