| /linux/include/linux/ |
| H A D | clk-provider.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
14 * top-level framework. custom flags for dealing with hardware specifics
20 #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
26 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
29 #define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */
31 /* parents need enable during gate/ungate, set rate and re-parent */
33 /* duty cycle call may be forwarded to the parent clock */
42 * struct clk_rate_request - Structure encoding the clk constraints that
[all …]
|
| /linux/drivers/clk/zynqmp/ |
| H A D | clkc.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Zynq UltraScale+ MPSoC clock controller
5 * Copyright (C) 2016-2019 Xilinx
12 #include <linux/clk-provider.h>
19 #include "clk-zynqmp.h"
49 * struct clock_parent - Clock parent
50 * @name: Parent name
51 * @id: Parent clock ID
55 char name[MAX_NAME_LEN]; member
61 * struct zynqmp_clock - Clock
[all …]
|
| H A D | clk-gate-zynqmp.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Zynq UltraScale+ MPSoC clock controller
5 * Copyright (C) 2016-2018 Xilinx
7 * Gated clock implementation
10 #include <linux/clk-provider.h>
12 #include "clk-zynqmp.h"
15 * struct zynqmp_clk_gate - gating clock
16 * @hw: handle between common and hardware-specific interfaces
17 * @flags: hardware-specific flags
18 * @clk_id: Id of clock
[all …]
|
| /linux/drivers/clk/samsung/ |
| H A D | clk.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
7 * Common Clock Framework support for all Samsung platforms
13 #include <linux/clk-provider.h>
14 #include "clk-pll.h"
15 #include "clk-cpu.h"
18 * struct samsung_clk_provider - information about clock provider
20 * @dev: clock provider device needed for runtime PM
21 * @lock: maintains exclusion between callbacks for a given clock-provider
22 * @clk_data: holds clock related data like clk_hw* and number of clocks
33 * struct samsung_clock_alias - information about mux clock
[all …]
|
| /linux/Documentation/devicetree/bindings/clock/ |
| H A D | xgene.txt | 1 Device Tree Clock bindings for APM X-Gene
3 This binding uses the common clock binding[1].
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be one of the following:
9 "apm,xgene-socpll-clock" - for a X-Gene SoC PLL clock
10 "apm,xgene-pcppll-clock" - for a X-Gene PCP PLL clock
11 "apm,xgene-pmd-clock" - for a X-Gene PMD clock
12 "apm,xgene-device-clock" - for a X-Gene device clock
13 "apm,xgene-socpll-v2-clock" - for a X-Gene SoC PLL v2 clock
14 "apm,xgene-pcppll-v2-clock" - for a X-Gene PCP PLL v2 clock
[all …]
|
| /linux/arch/arm/boot/dts/samsung/ |
| H A D | exynos4412-odroid-common.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 * Common definition for Hardkernel's Exynos4412 based ODROID-X/X2/U2/U3 boards
7 #include <dt-bindings/sound/samsung-i2s.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/clock/maxim,max77686.h>
11 #include "exynos4412-ppmu-common.dtsi"
12 #include <dt-bindings/gpio/gpio.h>
13 #include "exynos-mfc-reserved-memory.dtsi"
22 stdout-path = &serial_1;
26 compatible = "samsung,secure-firmware";
[all …]
|
| H A D | exynos4210-trats.dts | 1 // SPDX-License-Identifier: GPL-2.0
12 /dts-v1/;
14 #include <dt-bindings/gpio/gpio.h>
19 chassis-type = "handset";
37 stdout-path = "serial2:115200n8";
40 vemmc_reg: regulator-0 {
41 compatible = "regulator-fixed";
42 regulator-name = "VMEM_VDD_2.8V";
43 regulator-min-microvolt = <2800000>;
44 regulator-max-microvolt = <2800000>;
[all …]
|
| H A D | exynos4210-universal_c210.dts | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd.
12 /dts-v1/;
14 #include <dt-bindings/gpio/gpio.h>
19 chassis-type = "handset";
35 stdout-path = "serial2:115200n8";
39 fixed-rate-clocks {
41 compatible = "samsung,clock-xxti";
42 clock-frequency = <0>;
46 compatible = "samsung,clock-xusbxti";
[all …]
|
| H A D | exynos4210-i9100.dts | 1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos4210 based Galaxy S2 (GT-I9100 version) device tree
11 /dts-v1/;
13 #include "exynos4412-ppmu-common.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/input/linux-event-codes.h>
19 model = "Samsung Galaxy S2 (GT-I9100)";
21 chassis-type = "handset";
35 stdout-path = "serial2:115200n8";
38 vemmc_reg: regulator-0 {
[all …]
|
| /linux/drivers/isdn/mISDN/ |
| H A D | clock.c | 1 // SPDX-License-Identifier: GPL-2.0-only
7 * A clock source registers using mISDN_register_clock:
8 * name = text string to name clock source
9 * priority = value to priorize clock sources (0 = default)
10 * ctl = callback function to enable/disable clock source
11 * priv = private pointer of clock source
12 * return = pointer to clock source structure;
17 * A clock source calls mISDN_clock_update with given samples elapsed, if
21 * A clock source unregisters using mISDN_unregister_clock.
23 * To get current clock, call mISDN_clock_get. The signed short value
[all …]
|
| /linux/drivers/clk/uniphier/ |
| H A D | clk-uniphier-core.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
7 #include <linux/clk-provider.h>
13 #include "clk-uniphier.h"
19 switch (data->type) { in uniphier_clk_register()
21 return uniphier_clk_register_cpugear(dev, regmap, data->name, in uniphier_clk_register()
22 &data->data.cpugear); in uniphier_clk_register()
24 return uniphier_clk_register_fixed_factor(dev, data->name, in uniphier_clk_register()
25 &data->data.factor); in uniphier_clk_register()
27 return uniphier_clk_register_fixed_rate(dev, data->name, in uniphier_clk_register()
28 &data->data.rate); in uniphier_clk_register()
[all …]
|
| /linux/drivers/clk/ti/ |
| H A D | adpll.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 #include <linux/clk-provider.h>
179 const char *name; in ti_adpll_clk_get_name() local
183 err = of_property_read_string_index(d->np, in ti_adpll_clk_get_name()
184 "clock-output-names", in ti_adpll_clk_get_name()
186 &name); in ti_adpll_clk_get_name()
190 name = devm_kasprintf(d->dev, GFP_KERNEL, "%08lx.adpll.%s", in ti_adpll_clk_get_name()
191 d->pa, postfix); in ti_adpll_clk_get_name()
194 return name; in ti_adpll_clk_get_name()
199 static int ti_adpll_setup_clock(struct ti_adpll_data *d, struct clk *clock, in ti_adpll_setup_clock() argument
[all …]
|
| H A D | clk.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * TI clock support
7 * Tero Kristo <t-kristo@ti.com>
12 #include <linux/clk-provider.h>
25 #include "clock.h"
45 struct clk_iomap *io = clk_memmaps[reg->index]; in clk_memmap_writel()
47 if (reg->ptr) in clk_memmap_writel()
48 writel_relaxed(val, reg->ptr); in clk_memmap_writel()
49 else if (io->regmap) in clk_memmap_writel()
50 regmap_write(io->regmap, reg->offset, val); in clk_memmap_writel()
[all …]
|
| /linux/drivers/clk/renesas/ |
| H A D | clk-mstp.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car MSTP clocks
12 #include <linux/clk-provider.h>
26 * status register when enabling the clock.
32 * struct mstp_clock_group - MSTP gating clocks group
34 * @data: clock specifier translation for clocks in this group
38 * @width_8bit: registers are 8-bit, not 32-bit
51 * struct mstp_clock - MSTP gating clock
52 * @hw: handle between common and hardware-specific interfaces
67 return group->width_8bit ? readb(reg) : readl(reg); in cpg_mstp_read()
[all …]
|
| H A D | clk-div6.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * r8a7790 Common Clock Framework support
10 #include <linux/clk-provider.h>
20 #include "clk-div6.h"
27 * struct div6_clock - CPG 6 bit divider clock
28 * @hw: handle between common and hardware-specific interfaces
29 * @reg: IO-remapped register
30 * @div: divisor value (1-64)
31 * @src_mask: Bitmask covering the register bits to select the parent clock
32 * @nb: Notifier block to save/restore clock state for system resume
[all …]
|
| /linux/drivers/clk/ |
| H A D | clk-fixed-factor.c | 1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk-provider.h>
13 * DOC: basic fixed multiplier and divider clock that cannot gate
15 * Traits of this clock:
16 * prepare - clk_prepare only ensures that parents are prepared
17 * enable - clk_enable only ensures that parents are enabled
18 * rate - rate is fixed. clk->rate = parent->rate / div * mult
19 * parent - fixed parent. No clk_set_parent support
28 rate = (unsigned long long int)parent_rate * fix->mult; in clk_factor_recalc_rate()
29 do_div(rate, fix->div); in clk_factor_recalc_rate()
[all …]
|
| H A D | clk.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
6 * Standard functionality for the common clock API. See Documentation/driver-api/clk.rst
10 #include <linux/clk-provider.h>
11 #include <linux/clk/clk-conf.h>
56 const char *name; member
61 const char *name; member
116 if (!core->rpm_enabled) in clk_pm_runtime_get()
119 return pm_runtime_resume_and_get(core->dev); in clk_pm_runtime_get()
[all …]
|
| /linux/drivers/clk/bcm/ |
| H A D | clk-bcm2835.c | 1 // SPDX-License-Identifier: GPL-2.0+
8 * DOC: BCM2835 CPRMAN (clock manager for the "audio" domain)
10 * The clock tree on the 2835 has several levels. There's a root
22 * skip layers of the tree (for example, the pixel clock comes
23 * directly from the PLLH PIX channel without using a CM_*CTL clock
27 #include <linux/clk-provider.h>
38 #include <dt-bindings/clock/bcm2835.h>
45 # define CM_DIV_FRAC_MASK GENMASK(CM_DIV_FRAC_BITS - 1, 0)
253 # define A2W_PLL_FRAC_MASK ((1 << A2W_PLL_FRAC_BITS) - 1)
301 * with an external parent's name. This array is in the order that
[all …]
|
| H A D | clk-bcm63xx-gate.c | 1 // SPDX-License-Identifier: GPL-2.0
3 #include <linux/clk-provider.h>
8 #include <dt-bindings/clock/bcm3368-clock.h>
9 #include <dt-bindings/clock/bcm6318-clock.h>
10 #include <dt-bindings/clock/bcm6328-clock.h>
11 #include <dt-bindings/clock/bcm6358-clock.h>
12 #include <dt-bindings/clock/bcm6362-clock.h>
13 #include <dt-bindings/clock/bcm6368-clock.h>
14 #include <dt-bindings/clock/bcm63268-clock.h>
17 const char * const name; member
[all …]
|
| H A D | clk-kona-setup.c | 1 // SPDX-License-Identifier: GPL-2.0-only
10 #include "clk-kona.h"
13 #define selector_clear_exists(sel) ((sel)->width = 0)
20 struct ccu_policy *ccu_policy = &ccu->policy; in ccu_data_offsets_valid()
23 limit = ccu->range - sizeof(u32); in ccu_data_offsets_valid()
26 if (ccu_policy->enable.offset > limit) { in ccu_data_offsets_valid()
29 ccu->name, ccu_policy->enable.offset, limit); in ccu_data_offsets_valid()
32 if (ccu_policy->control.offset > limit) { in ccu_data_offsets_valid()
35 ccu->name, ccu_policy->control.offset, limit); in ccu_data_offsets_valid()
45 struct peri_clk_data *peri = bcm_clk->u.peri; in clk_requires_trigger()
[all …]
|
| /linux/drivers/platform/x86/intel/int3472/ |
| H A D | clk_and_regulator.c | 1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk-provider.h>
16 * 82c0d13a-78c5-4244-9bb1-eb8b539a8d11
30 if (clk->ena_gpio) { in skl_int3472_enable_clk()
31 gpiod_set_value_cansleep(clk->ena_gpio, enable); in skl_int3472_enable_clk()
36 args[0].integer.value = clk->imgclk_index; in skl_int3472_enable_clk()
46 acpi_evaluate_dsm(acpi_device_handle(int3472->adev), &img_clk_guid, in skl_int3472_enable_clk()
71 * We're just turning a GPIO on to enable the clock, which operation in skl_int3472_clk_enable()
89 obj = skl_int3472_get_acpi_buffer(int3472->sensor, "SSDB"); in skl_int3472_get_clk_frequency()
93 if (obj->buffer.length < CIO2_SENSOR_SSDB_MCLKSPEED_OFFSET + sizeof(u32)) { in skl_int3472_get_clk_frequency()
[all …]
|
| /linux/arch/arm64/boot/dts/amlogic/ |
| H A D | meson-g12.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include "meson-g12-common.dtsi"
8 #include <dt-bindings/clock/axg-audio-clkc.h>
9 #include <dt-bindings/power/meson-g12a-power.h>
10 #include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h>
11 #include <dt-bindings/reset/amlogic,meson-g12a-audio-reset.h>
14 tdmif_a: audio-controller-0 {
15 compatible = "amlogic,axg-tdm-iface";
16 #sound-dai-cells = <0>;
17 sound-name-prefix = "TDM_A";
[all …]
|
| /linux/tools/testing/selftests/vDSO/ |
| H A D | vdso_test_correctness.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * ldt_gdt.c - Test cases for LDT and GDT access
4 * Copyright (c) 2011-2015 Andrew Lutomirski
26 static const char **name; variable
47 /* max length of lines in /proc/self/maps - anything longer is skipped here */
83 char name[MAPS_LINE_LEN]; in vsyscall_getcpu() local
85 /* sscanf() is safe here as strlen(name) >= strlen(line) */ in vsyscall_getcpu()
86 if (sscanf(line, "%p-%p %c-%cp %*x %*x:%*x %*u %s", in vsyscall_getcpu()
87 &start, &end, &r, &x, name) != 5) in vsyscall_getcpu()
90 if (strcmp(name, "[vsyscall]")) in vsyscall_getcpu()
[all …]
|
| /linux/Documentation/devicetree/bindings/clock/ti/davinci/ |
| H A D | pll.txt | 5 an multiplexers for various clock signals.
8 - compatible: shall be one of:
9 - "ti,da850-pll0" for PLL0 on DA850/OMAP-L138/AM18XX
10 - "ti,da850-pll1" for PLL1 on DA850/OMAP-L138/AM18XX
11 - reg: physical base address and size of the controller's register area.
12 - clocks: phandles corresponding to the clock names
13 - clock-names: names of the clock sources - depends on compatible string
14 - for "ti,da850-pll0", shall be "clksrc", "extclksrc"
15 - for "ti,da850-pll1", shall be "clksrc"
18 - ti,clkmode-square-wave: Indicates that the board is supplying a square
[all …]
|
| /linux/Documentation/devicetree/bindings/display/ |
| H A D | allwinner,sun8i-r40-tcon-top.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/allwinner,sun8i-r40-tcon-top.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
17 encoder clock source and contains additional TV TCON and DSI gates.
22 / [0] TCON-LCD0
25 \ / [1] TCON-LCD1 - LCD1/LVDS1
26 TCON-TOP
[all …]
|