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/linux/Documentation/devicetree/bindings/sound/
H A Dfsl,ssi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shengjiu Wang <shengjiu.wang@nxp.com>
13 Notes on fsl,playback-dma and fsl,capture-dma
14 On SOCs that have an SSI, specific DMA channels are hard-wired for playback
18 DMA controller to use, but the channels themselves are hard-wired. The
22 "fsl,playback-dma" and "fsl,capture-dma" must be marked as compatible with
23 "fsl,ssi-dma-channel". The SOC-specific compatible string (e.g.
24 "fsl,mpc8610-dma-channel") can remain. If these nodes are left as
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H A Dmediatek,mt2701-audio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/mediatek,mt2701-audio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
13 - Eugen Hristev <eugen.hristev@collabora.com>
18 - mediatek,mt2701-audio
19 - mediatek,mt7622-audio
23 - description: AFE interrupt
24 - description: ASYS interrupt
26 interrupt-names:
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H A Dfsl,sai.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shengjiu Wang <shengjiu.wang@nxp.com>
21 - items:
22 - enum:
23 - fsl,imx6ul-sai
24 - fsl,imx7d-sai
25 - const: fsl,imx6sx-sai
27 - items:
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H A Damlogic,aiu.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jerome Brunet <jbrunet@baylibre.com>
13 - $ref: dai-common.yaml#
17 pattern: "^audio-controller@.*"
19 "#sound-dai-cells":
24 - enum:
25 - amlogic,aiu-gxbb
26 - amlogic,aiu-gxl
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/linux/Documentation/devicetree/bindings/i3c/
H A Dsilvaco,i3c-master.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/i3c/silvaco,i3c-master.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Silvaco I3C master
10 - Conor Culhane <conor.culhane@silvaco.com>
15 - enum:
16 - nuvoton,npcm845-i3c
17 - silvaco,i3c-master-v1
18 - items:
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H A Dsnps,dw-i3c-master.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/i3c/snps,dw-i3c-master.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare I3C master block
10 - Alexandre Belloni <alexandre.belloni@bootlin.com>
13 - $ref: i3c.yaml#
18 - const: snps,dw-i3c-master-1.00a
19 - items:
20 - const: altr,agilex5-dw-i3c-master
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H A Dcdns,i3c-master.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/i3c/cdns,i3c-master.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence I3C master block
10 - Boris Brezillon <bbrezillon@kernel.org>
13 - $ref: i3c.yaml#
18 - const: cdns,i3c-master
19 - items:
20 - enum:
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/linux/Documentation/devicetree/bindings/ata/
H A Dcortina,gemini-sata-bridge.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/cortina,gemini-sata-bridge.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linusw@kernel.org>
13 The Gemini SATA bridge in a SoC-internal PATA to SATA bridge that
19 const: cortina,gemini-sata-bridge
28 reset-names:
30 - const: sata0
31 - const: sata1
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/linux/sound/soc/mxs/
H A Dmxs-saif.c1 // SPDX-License-Identifier: GPL-2.0-or-later
11 #include <linux/dma-mapping.h>
13 #include <linux/clk-provider.h>
22 #include "mxs-saif.h"
33 * is provided by other SAIF, we provide a interface here to get its master
35 * Note that the master coul
730 struct device_node *master; mxs_saif_probe() local
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/linux/arch/arm64/boot/dts/axiado/
H A Dax3000.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2021-25 Axiado Corporation (or its affiliates). All rights reserved.
6 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 /memreserve/ 0x3c0013a0 0x00000008; /* cpu-release-addr */
14 interrupt-parent = <&gic500>;
15 #address-cells = <2>;
16 #size-cells = <2>;
19 #address-cells = <2>;
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/linux/sound/soc/atmel/
H A Datmel-i2s.c1 // SPDX-License-Identifier: GPL-2.0-only
29 * ---- I2S Controller Register map ----
44 * ---- Control Register (Write-only) ----
48 #define ATMEL_I2SC_CR_CKEN BIT(2) /* Clock Enable */
49 #define ATMEL_I2SC_CR_CKDIS BIT(3) /* Clock Disable */
55 * ---- Mode Register (Read/Write) ----
101 /* Audio Clock to I2SC Master Clock ratio */
106 /* Master Clock to fs ratio */
111 /* Master Clock mode */
113 /* 0: No master clock generated (selected clock drives I2SCK pin) */
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/linux/Documentation/devicetree/bindings/clock/
H A Dnxp,imx95-display-master-csr.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/nxp,imx95-display-master-csr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX95 Display Master Block Control
10 - Peng Fan <peng.fan@nxp.com>
15 - const: nxp,imx95-display-master-csr
16 - const: syscon
21 power-domains:
27 '#clock-cells':
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H A Dbrcm,kona-ccu.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/brcm,kona-ccu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom Kona family clock control units (CCU)
10 - Florian Fainelli <florian.fainelli@broadcom.com>
11 - Ray Jui <rjui@broadcom.com>
12 - Scott Branden <sbranden@broadcom.com>
15 Broadcom "Kona" style clock control unit (CCU) is a clock provider that
16 manages a set of clock signals.
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/linux/Documentation/i2c/
H A Dgpio-fault-injection.rst5 The GPIO based I2C bus master driver can be configured to provide fault
7 which is driven by the I2C bus master driver under test. The GPIO fault
9 master driver should handle gracefully.
12 'i2c-fault-injector' subdirectory in the Kernel debugfs filesystem, usually
15 injection. They will be described now along with their intended use-cases.
21 -----
26 because the bus master under test will not be able to clock. It should detect
31 -----
36 master under test should detect this condition and trigger a bus recovery (see
52 in a bus master driver, make sure you checked your hardware setup for such
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/linux/Documentation/ABI/testing/
H A Dsysfs-bus-soundwire-master1 What: /sys/bus/soundwire/devices/sdw-master-<N>/revision
2 /sys/bus/soundwire/devices/sdw-master-<N>/clk_stop_modes
3 /sys/bus/soundwire/devices/sdw-master-<N>/clk_freq
4 /sys/bus/soundwire/devices/sdw-master-<N>/clk_gears
5 /sys/bus/soundwire/devices/sdw-master-<N>/default_col
6 /sys/bus/soundwire/devices/sdw-master-<N>/default_frame_rate
7 /sys/bus/soundwire/devices/sdw-master-<N>/default_row
8 /sys/bus/soundwire/devices/sdw-master-<N>/dynamic_shape
9 /sys/bus/soundwire/devices/sdw-master-<N>/err_threshold
10 /sys/bus/soundwire/devices/sdw-master-<N>/max_clk_freq
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/linux/include/linux/clk/
H A Dat91_pmc.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
8 * Power Management Controller (PMC) - System peripherals registers.
20 #define AT91_PMC_SCER 0x00 /* System Clock Enable Register */
21 #define AT91_PMC_SCDR 0x04 /* System Clock Disable Register */
23 #define AT91_PMC_SCSR 0x08 /* System Clock Status Register */
24 #define AT91_PMC_PCK (1 << 0) /* Processor Clock */
25 #define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */
26 #define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Susp…
27 #define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */
28 #define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */
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/linux/Documentation/devicetree/bindings/fsi/
H A Daspeed,ast2600-fsi-master.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fsi/aspeed,ast2600-fsi-master.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Aspeed FSI master
10 - Eddie James <eajames@linux.ibm.com>
14 clock and have a separate interrupt line and output pins.
19 - aspeed,ast2600-fsi-master
20 - aspeed,ast2700-fsi-master
25 cfam-reset-gpios:
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/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1012a-frdm.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include "fsl-ls1012a.dtsi"
15 compatible = "fsl,ls1012a-frdm", "fsl,ls1012a";
17 sys_mclk: clock-mclk {
18 compatible = "fixed-clock";
19 #clock-cells = <0>;
20 clock-frequency = <25000000>;
23 sc16is7xx_clk: clock-sc16is7xx {
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H A Dfsl-ls1012a-oxalis.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 /dts-v1/;
11 #include "fsl-ls1012a.dtsi"
15 compatible = "ebs-systart,oxalis", "fsl,ls1012a";
17 sys_mclk: clock-mclk {
18 compatible = "fixed-clock";
19 #clock-cells = <0>;
20 clock-frequency = <25000000>;
23 reg_1p8v: regulator-1p8v {
24 compatible = "regulator-fixed";
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/linux/arch/arm/boot/dts/samsung/
H A Dexynos5420.dtsi1 // SPDX-License-Identifier: GPL-2.0
14 #include <dt-bindings/clock/exynos5420.h>
15 #include <dt-bindings/clock/exynos-audss-clk.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
37 bus_disp1: bus-disp1 {
38 compatible = "samsung,exynos-bus";
39 clocks = <&clock CLK_DOUT_ACLK400_DISP1>;
40 clock-names = "bus";
44 bus_disp1_fimd: bus-disp1-fimd {
45 compatible = "samsung,exynos-bus";
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/linux/Documentation/devicetree/bindings/display/bridge/
H A Dsynopsys,dw-hdmi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/synopsys,dw-hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
16 bindings for the platform-specific integrations of the DWC HDMI TX.
26 reg-io-width:
36 - description: The bus clock for either AHB and APB
37 - description: The internal register configuration clock
40 clock-names:
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/linux/Documentation/devicetree/bindings/spi/
H A Dicpdas-lp8841-spi-rtc.txt1 * ICP DAS LP-8841 SPI Controller for RTC
3 ICP DAS LP-8841 contains a DS-1302 RTC. RTC is connected to an IO
4 memory register, which acts as an SPI master device.
6 The device uses the standard MicroWire half-duplex transfer timing.
7 Master output is set on low clock and sensed by the RTC on the rising
8 edge. Master input is set by the RTC on the trailing edge and is sensed
9 by the master on low clock.
13 - #address-cells: should be 1
15 - #size-cells: should be 0
17 - compatible: should be "icpdas,lp8841-spi-rtc"
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/linux/Documentation/devicetree/bindings/dma/
H A Darm-pl08x.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/arm-pl08x.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vinod Koul <vkoul@kernel.org>
13 - $ref: /schemas/arm/primecell.yaml#
14 - $ref: dma-controller.yaml#
22 - arm,pl080
23 - arm,pl081
25 - compatible
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/linux/Documentation/devicetree/bindings/soc/qcom/
H A Dqcom,geni-se.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/qcom/qcom,geni-se.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
23 - qcom,geni-se-qup
24 - qcom,geni-se-i2c-master-hub
30 clock-names:
38 "#address-cells":
41 "#size-cells":
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/linux/drivers/ata/
H A Dpata_pdc202xx_old.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * pata_pdc202xx_old.c - Promise PDC202xx PATA for new ATA layer
29 struct pci_dev *pdev = to_pci_dev(ap->host->dev); in pdc2026x_cable_detect()
33 if (cis & (1 << (10 + ap->port_no))) in pdc2026x_cable_detect()
41 iowrite8(tf->command, ap->ioaddr.command_addr); in pdc202xx_exec_command()
47 struct pci_dev *pdev = to_pci_dev(ap->host->dev); in pdc202xx_irq_check()
48 unsigned long master = pci_resource_start(pdev, 4); in pdc202xx_irq_check() local
49 u8 sc1d = inb(master + 0x1d); in pdc202xx_irq_check()
51 if (ap->port_no) { in pdc202xx_irq_check()
67 * pdc202xx_configure_piomode - set chip PIO timing
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