Home
last modified time | relevance | path

Searched +full:clock +full:- +full:frequency (Results 1 – 25 of 1033) sorted by relevance

12345678910>>...42

/freebsd/sys/contrib/device-tree/Bindings/i2c/
H A Di2c-ocores.txt1 Device tree configuration for i2c-ocores
4 - compatible : "opencores,i2c-ocores"
6 "sifive,fu540-c000-i2c", "sifive,i2c0"
8 FU540-C000 SoC.
9 "sifive,fu740-c000-i2c", "sifive,i2c0"
11 FU740-C000 SoC.
12 Please refer to sifive-blocks-ip-versioning.txt for
14 - reg : bus address start and address range size of device
15 - clocks : handle to the controller clock; see the note below.
16 Mutually exclusive with opencores,ip-clock-frequency
[all …]
H A Dopencores,i2c-ocores.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/opencores,i2c-ocores.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Peter Korsgaard <peter@korsgaard.com>
11 - Andrew Lunn <andrew@lunn.ch>
14 - $ref: /schemas/i2c/i2c-controller.yaml#
19 - items:
20 - enum:
21 - sifive,fu740-c000-i2c # Opencore based IP block FU740-C000 SoC
[all …]
/freebsd/share/man/man7/
H A Dclocks.743 .Bl -bullet
45 The scheduling clock.
46 This is a real clock with frequency that happens to be 100.
49 The statistics clock.
50 This is a real clock with frequency that happens to be 128.
53 The clock reported by
54 .Xr clock 3 .
55 This is a virtual clock with a frequency that happens to be 128.
56 Its actual frequency is given by the macro
62 .Xr clock 3
[all …]
/freebsd/sys/contrib/device-tree/src/arm/broadcom/
H A Dbcm11351.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (C) 2012-2013 Broadcom Corporation
4 #include <dt-bindings/clock/bcm281xx.h>
5 #include <dt-bindings/interrupt-controller/arm-gi
[all...]
H A Dbcm2166x-common.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
9 /dts-v1/;
11 #include <dt-bindings/clock/bcm21664.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
16 #address-cells = <1>;
17 #size-cells = <1>;
20 hub: hub-bus@34000000 {
21 compatible = "simple-bus";
23 #address-cells = <1>;
[all …]
/freebsd/contrib/ntp/html/
H A Ddiscipline.html1 <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
4 <meta http-equiv="content-type" content="text/html;charset=iso-8859-1">
6 <title>Clock Discipline Algorithm</title>
7 <!-- Changed by: stenn, 03-Jan-2020 -->
11 <h3>Clock Discipline Algorithm</h3>
13 <!-- #BeginDate format:En2m -->3-Jan-2020 02:12<!-- #EndDate -->
18 <li class="inline"><a href="#pll">Phase-Lock Loop Operations</a></li>
20 <li class="inline"><a href="#house">Clock Initialization and Management</a></li>
24 …clock discipline algorithm, which is best described as an adaptive parameter, hybrid phase/frequen…
26 <p>Figure 1. Clock Discipline Algorithm</p>
[all …]
H A Dclock.html1 <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
4 <meta http-equiv="content-type" content="text/html;charset=iso-8859-1">
6 <title>Clock State Machine</title>
10 <h3>Clock State Machine</h3>
12 <!-- #BeginDate format:En2m -->4-Aug-2011 23:40<!-- #EndDate -->
25 …and reference implementation a state machine is used to manage the system clock under exceptional …
26 … the clock discipline algorithm. its primary purpose is to determines whether the clock is slewed …
28 …-of-year (TOY) chip to maintain the time when the power is off. When the computer is restarted, t…
30 …clock discipline gradually slews the clock to the correct time, so that the time is effectively co…
31 …ed and the clock is always slewed. The daemon sets the step threshold to 600 s using the <tt>-x</t…
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/amd/
H A Damd-seattle-clks.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 compatible = "fixed-clock";
10 #clock-cells = <0>;
11 clock-frequency = <100000000>;
12 clock-output-names = "adl3clk_100mhz";
16 compatible = "fixed-clock";
17 #clock-cells = <0>;
18 clock-frequency = <375000000>;
19 clock-output-names = "ccpclk_375mhz";
23 compatible = "fixed-clock";
[all …]
/freebsd/sys/contrib/device-tree/src/arm/intel/axm/
H A Daxm5516-cpus.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * arch/arm/boot/dts/axm5516-cpus.dtsi
10 #address-cells = <1>;
11 #size-cells = <0>;
13 cpu-map {
74 compatible = "arm,cortex-a15";
76 clock-frequency = <1400000000>;
77 cpu-release-addr = <0>; // Fixed by the boot loader
82 compatible = "arm,cortex-a15";
84 clock-frequency = <1400000000>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dnvidia,tegra124-car.txt1 NVIDIA Tegra124 and Tegra132 Clock And Reset Controller
3 This binding uses the common clock binding:
4 Documentation/devicetree/bindings/clock/clock-bindings.txt
6 The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
10 - compatible : Should be "nvidia,tegra124-car" or "nvidia,tegra132-car"
11 - reg : Should contain CAR registers location and length
12 - clocks : Should contain phandle and clock specifiers for two clocks:
13 the 32 KHz "32k_in", and the board-specific oscillator "osc".
14 - #clock-cells : Should be 1.
15 In clock consumers, this cell represents the clock ID exposed by the
[all …]
H A Dqoriq-clock.txt1 * Clock Block on Freescale QorIQ Platforms
4 SYSCLK signal. The SYSCLK input (frequency) is multiplied using
14 --------------- -------------
18 1. Clock Block Binding
21 - compatible: Should contain a chip-specific clock block compatible
22 string and (if applicable) may contain a chassis-version clock
25 Chip-specific strings are of the form "fsl,<chip>-clockgen", such as:
26 * "fsl,p2041-clockgen"
27 * "fsl,p3041-clockgen"
28 * "fsl,p4080-clockgen"
[all …]
H A Dnuvoton,npcm750-clk.txt1 * Nuvoton NPCM7XX Clock Controller
3 Nuvoton Poleg BMC NPCM7XX contains an integrated clock controller, which
10 clk_sysbypck are inputs to the clock controller.
12 network. They are set on the device tree, but not used by the clock module. The
17 dt-bindings/clock/nuvoton,npcm7xx-clock.h
20 Required Properties of clock controller:
22 - compatible: "nuvoton,npcm750-clk" : for clock controller of Nuvoton
25 - reg: physical base address of the clock controller and length of
28 - #clock-cells: should be 1.
30 Example: Clock controller node:
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/zte/
H A Dzx296718.dtsi5 * This file is dual-licensed: you can use it either under the terms
44 #include <dt-bindings/input/input.h>
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/gpio/gpio.h>
47 #include <dt-bindings/clock/zx296718-clock.h>
51 #address-cells = <1>;
52 #size-cells = <1>;
53 interrupt-parent = <&gic>;
67 #address-cells = <2>;
68 #size-cells = <0>;
[all …]
/freebsd/lib/libsys/
H A Dntp_adjtime.255 function is used by the NTP daemon to adjust the system clock to an
61 to adjust the phase and frequency of the phase- or frequency-lock loop
62 (PLL resp. FLL) which controls the system clock.
78 .Bd -literal
80 unsigned int modes; /* clock mode bits (wo) */
82 long freq; /* frequency offset (scaled ppm) (rw) */
85 int status; /* clock status bits (rw) */
87 long precision; /* clock precision (us) (ro) */
88 long tolerance; /* clock frequency tolerance (scaled
91 * The following read-only structure members are implemented
[all …]
/freebsd/contrib/ntp/ntpd/
H A Dntpd-opts.def1 /* -*- Mode: Text -*- */
7 prog-name = "ntpd";
8 prog-title = "set clock via Network Time Protocol daemon";
11 #include ntpdbase-opts.def
14 explain = <<- _END_EXPLAIN
17 doc-section = {
18 ds-type = 'DESCRIPTION';
19 ds-format = 'mdoc';
20 ds-text = <<- _END_PROG_MDOC_DESCRIP
27 Network Time Protocol (NTP) version 4, as defined by RFC-5905,
[all …]
/freebsd/sys/contrib/device-tree/src/nios2/
H A D10m50_devboard.dts1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
10 compatible = "altr,niosii-max10";
11 #address-cells = <1>;
12 #size-cells = <1>;
15 #address-cells = <1>;
16 #size-cells = <0>;
20 compatible = "altr,nios2-1.1";
22 interrupt-controller;
23 #interrupt-cells = <1>;
[all …]
/freebsd/sys/contrib/device-tree/src/arc/
H A Dhsdk.dts1 // SPDX-License-Identifier: GPL-2.0-only
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/reset/snps,hsdk-reset.h>
18 #address-cells = <2>;
19 #size-cells = <2>;
22 … "earlycon=uart8250,mmio32,0xf0005000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1";
30 #address-cells = <1>;
31 #size-cells = <0>;
62 input_clk: input-clk {
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nvidia/
H A Dtegra124-apalis-emc.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR X11
3 * Copyright 2016-2019 Toradex AG
7 #include <dt-bindings/clock/tegra124-car.h>
10 clock@60006000 {
11 emc-timings-1 {
12 nvidia,ram-code = <1>;
14 timing-12750000 {
15 clock-frequency = <12750000>;
16 nvidia,parent-clock-frequency = <408000000>;
18 clock-names = "emc-parent";
[all …]
H A Dtegra124-jetson-tk1-emc.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/clock/tegra124-car.h>
6 clock@60006000 {
7 emc-timings-3 {
8 nvidia,ram-code = <3>;
10 timing-12750000 {
11 clock-frequency = <12750000>;
12 nvidia,parent-clock-frequency = <408000000>;
14 clock-names = "emc-parent";
17 timing-20400000 {
[all …]
H A Dtegra124-nyan-blaze-emc.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/clock/tegra124-car.h>
6 clock@60006000 {
7 emc-timings-1 {
8 nvidia,ram-code = <1>;
10 timing-12750000 {
11 clock-frequency = <12750000>;
12 nvidia,parent-clock-frequency = <408000000>;
14 clock-names = "emc-parent";
17 timing-20400000 {
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/arm/
H A Djuno-clocks.dtsi4 * Copyright (c) 2013-2014 ARM Ltd
11 soc_uartclk: clock-7372800 {
12 compatible = "fixed-clock";
13 #clock-cells = <0>;
14 clock-frequency = <7372800>;
15 clock-output-names = "juno:uartclk";
18 soc_usb48mhz: clock-48000000 {
19 compatible = "fixed-clock";
20 #clock-cells = <0>;
21 clock-frequency = <48000000>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/display/exynos/
H A Dexynos_dsim.txt4 - compatible: value should be one of the following
5 "samsung,exynos3250-mipi-dsi" /* for Exynos3250/3472 SoCs */
6 "samsung,exynos4210-mipi-dsi" /* for Exynos4 SoCs */
7 "samsung,exynos5410-mipi-dsi" /* for Exynos5410/5420/5440 SoCs */
8 "samsung,exynos5422-mipi-dsi" /* for Exynos5422/5800 SoCs */
9 "samsung,exynos5433-mipi-dsi" /* for Exynos5433 SoCs */
10 - reg: physical base address and length of the registers set for the device
11 - interrupts: should contain DSI interrupt
12 - clocks: list of clock specifiers, must contain an entry for each required
13 entry in clock-names
[all …]
/freebsd/sys/contrib/device-tree/Bindings/display/bridge/
H A Dsamsung,mipi-dsim.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/samsung,mipi-dsim.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Inki Dae <inki.dae@samsung.com>
11 - Jagan Teki <jagan@amarulasolutions.com>
12 - Marek Szyprowski <m.szyprowski@samsung.com>
21 - enum:
22 - samsung,exynos3250-mipi-dsi
23 - samsung,exynos4210-mipi-dsi
[all …]
/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/
H A Drockchip,rk3399-dmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controller
[all...]
/freebsd/sys/contrib/device-tree/Bindings/net/wireless/
H A Dti,wlcore.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tony Lindgren <tony@atomide.com>
14 Note that the *-clock-frequency properties assume internal clocks. In case
15 of external clocks, new bindings (for parsing the clock nodes) have to be
21 - ti,wl1271
22 - ti,wl1273
23 - ti,wl1281
24 - ti,wl1283
[all …]

12345678910>>...42