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/linux/Documentation/devicetree/bindings/clock/
H A Dfixed-clock.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/fixed-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Simple fixed-rate clock sources
10 - Michael Turquette <mturquette@baylibre.com>
11 - Stephen Boyd <sboyd@kernel.org>
16 - description:
17 Preferred name is 'clock-<freq>' with <freq> being the output
18 frequency as defined in the 'clock-frequency' property.
[all …]
/linux/drivers/clk/
H A Dclk-fixed-rate.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
6 * Fixed rate clock implementation
9 #include <linux/clk-provider.h>
18 * DOC: basic fixed-rate clock that cannot gate
20 * Traits of this clock:
21 * prepare - clk_(un)prepare only ensures parents are prepared
22 * enable - clk_enable only ensures parents are enabled
23 * rate - rate is always a fixed value. No clk_set_rate support
[all …]
H A Dkunit_clk_fixed_rate_test.dtso1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
5 #include "clk-fixed-rate_test.h"
8 fixed_50MHz: kunit-clock {
9 compatible = "fixed-clock";
10 #clock-cells = <0>;
11 clock-frequency = <TEST_FIXED_FREQUENCY>;
12 clock-accuracy = <TEST_FIXED_ACCURACY>;
15 kunit-clock-consumer {
16 compatible = "test,single-clk-consumer";
H A Dclk.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
6 * Standard functionality for the common clock API. See Documentation/driver-api/clk.rst
9 #include <linux/clk/clk-conf.h>
12 #include <linux/clk-provider.h>
67 * struct clk_core - The internal state of a clk in the clk tree.
69 * @ops: Pointer to hardware-specific operations for this clk.
71 * corresponding hardware-specific structure.
76 * @parent: Pointer to the current parent in the clock tree.
[all …]
/linux/Documentation/timers/
H A Dtimekeeping.rst2 Clock sources, Clock events, sched_clock() and delay timers
10 If you grep through the kernel source you will find a number of architecture-
11 specific implementations of clock sources, clockevents and several likewise
12 architecture-specific overrides of the sched_clock() function and some
15 To provide timekeeping for your platform, the clock source provides
16 the basic timeline, whereas clock events shoot interrupts on certain points
17 on this timeline, providing facilities such as high-resolution timers.
22 Clock sources
23 -------------
25 The purpose of the clock source is to provide a timeline for the system that
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/linux/Documentation/hwmon/
H A Dpc87360.rst22 -----------------
27 - 0: None
28 - **1**: Forcibly enable internal voltage and temperature channels,
30 - 2: Forcibly enable all voltage and temperature channels, except in9
31 - 3: Forcibly enable all voltage and temperature channels, including in9
42 -----------
56 PC87360 - 2 2 - 0xE1
57 PC87363 - 2 2 - 0xE8
58 PC87364 - 3 3 - 0xE4
60 PC87366 11 3 3 3-4 0xE9
[all …]
H A Dshtc1.rst41 -----------
48 address 0x70. See Documentation/i2c/instantiating-devices.rst for methods to
53 1. blocking (pull the I2C clock line down while performing the measurement) or
54 non-blocking mode. Blocking mode will guarantee the fastest result but
55 the I2C bus will be busy during that time. By default, non-blocking mode
56 is used. Make sure clock-stretching works properly on your device if you
58 2. high or low accuracy. High accuracy is used by default and using it is
61 sysfs-Interface
62 ---------------
65 - temperature input
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/linux/include/linux/
H A Dclk-provider.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
9 #include <dt-bindings/clock/clock.h>
17 * top-level framework. Custom flags for dealing with hardware specifics
20 * * CLK_SET_RATE_GATE - must be gated across rate change
21 * * CLK_SET_PARENT_GATE - must be gated across re-parent
22 * * CLK_SET_RATE_PARENT - propagate rate change up one level
23 * * CLK_IGNORE_UNUSED - do not gate even if unused
24 * * CLK_GET_RATE_NOCACHE - do not use the cached clk rate
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/linux/arch/arm/boot/dts/alphascale/
H A Dalphascale-asm9260.dtsi2 * Copyright 2014 Oleksij Rempel <linux@rempel-privat.de>
7 #include <dt-bindings/clock/alphascale,asm9260.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
12 interrupt-parent = <&icoll>;
20 #address-cells = <0>;
21 #size-cells = <0>;
24 compatible = "arm,arm926ej-s";
31 compatible = "fixed-clock";
32 #clock-cells = <0>;
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/linux/Documentation/sound/designs/
H A Dtimestamping.rst7 - Trigger_tstamp is the system time snapshot taken when the .trigger
11 estimate with a delay. In the latter two cases, the low-level driver
17 - tstamp is the current system timestamp updated during the last
19 The difference (tstamp - trigger_tstamp) defines the elapsed time.
29 - ``avail`` reports how much can be written in the ring buffer
30 - ``delay`` reports the time it will take to hear a new sample after all
43 ascii-art, this could be represented as follows (for the playback
47 --------------------------------------------------------------> time
53 |< codec delay >|<--hw delay-->|<queued samples>|<---avail->|
54 |<----------------- delay---------------------->| |
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/linux/arch/arm/boot/dts/intel/pxa/
H A Dpxa300-raumfeld-tuneable-clock.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/clock/maxim,max9485.h>
6 xo_27mhz: oscillator-27mhz {
7 compatible = "fixed-clock";
8 #clock-cells = <0>;
9 clock-frequency = <27000000>;
10 clock-accuracy = <100>;
14 compatible = "simple-audio-card";
15 simple-audio-card,name = "Raumfeld Speaker";
16 #address-cells = <1>;
[all …]
H A Dpxa300-raumfeld-speaker-one.dts1 // SPDX-License-Identifier: GPL-2.0
3 /dts-v1/;
5 #include "pxa300-raumfeld-common.dtsi"
9 compatible = "raumfeld,raumfeld-speaker-one-pxa303", "marvell,pxa300";
13 #sound-dai-cells = <0>;
14 Vdd-supply = <&reg_3v3>;
15 Vdda-supply = <&reg_va_5v0>;
18 xo_11mhz: oscillator-11mhz {
19 compatible = "fixed-clock";
20 #clock-cells = <0>;
[all …]
/linux/drivers/clk/at91/
H A Ddt-compat.c1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/clk-provider.h>
34 const char *name = np->name; in of_sama5d2_clk_audio_pll_frac_setup()
54 "atmel,sama5d2-clk-audio-pll-frac",
60 const char *name = np->name; in of_sama5d2_clk_audio_pll_pad_setup()
80 "atmel,sama5d2-clk-audio-pll-pad",
86 const char *name = np->name; in of_sama5d2_clk_audio_pll_pmc_setup()
106 "atmel,sama5d2-clk-audio-pll-pmc",
162 if (of_property_read_string(np, "clock-output-names", &name)) in of_sama5d2_clk_generated_setup()
163 name = gcknp->name; in of_sama5d2_clk_generated_setup()
[all …]
H A Dsckc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 #include <linux/clk-provider.h>
15 #include <dt-bindings/clock/at91.h>
55 unsigned long accuracy; member
73 void __iomem *sckcr = osc->sckcr; in clk_slow_osc_prepare()
76 if (tmp & (osc->bits->cr_osc32byp | osc->bits->cr_osc32en)) in clk_slow_osc_prepare()
79 writel(tmp | osc->bits->cr_osc32en, sckcr); in clk_slow_osc_prepare()
82 udelay(osc->startup_usec); in clk_slow_osc_prepare()
84 usleep_range(osc->startup_usec, osc->startup_usec + 1); in clk_slow_osc_prepare()
92 void __iomem *sckcr = osc->sckcr; in clk_slow_osc_unprepare()
[all …]
/linux/drivers/video/fbdev/kyro/
H A DSTG4000InitDevice.c41 /* Core clock freq */
44 /* Reference Clock freq */
61 /* PLL Clock */
101 /* Program SD-RAM interface */ in InitSDRAMRegisters()
129 /* Translate clock in Hz */ in ProgramClock()
133 /* Work out acceptable clock in ProgramClock()
134 * The method calculates ~ +- 0.4% (1/256) in ProgramClock()
136 ulMinClock = coreClock - (coreClock >> 8); in ProgramClock()
139 /* Scale clock required for use in calculations */ in ProgramClock()
147 /* loop for pre-divider from min to max */ in ProgramClock()
[all …]
/linux/Documentation/devicetree/bindings/iio/adc/
H A Drenesas,r9a09g077-adc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/renesas,r9a09g077-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
13 A/D Converter block is a successive approximation analog-to-digital converter
14 with a 12-bit accuracy. Up to 16 analog input channels can be selected.
16 is stored in a 16-bit data register corresponding to each channel.
21 - items:
22 - const: renesas,r9a09g087-adc # RZ/N2H
[all …]
H A Dti,adc12138.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Texas Instruments ADC12138 and similar self-calibrating ADCs
10 - Akinobu Mita <akinobu.mita@gmail.com>
19 - ti,adc12130
20 - ti,adc12132
21 - ti,adc12138
32 description: Conversion clock input.
34 vref-p-supply:
[all …]
/linux/tools/testing/selftests/kvm/x86/
H A Dhyperv_clock.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Tests for Hyper-V clocksources
59 /* For increased accuracy, take mean rdtsc() before and after rdmsr() */ in check_tsc_msr_rdtsc()
71 delta_ns = ((t2 - t1) * 100) - ((r2 - r1) * 1000000000 / tsc_freq); in check_tsc_msr_rdtsc()
73 delta_ns = -delta_n in check_tsc_msr_rdtsc()
255 struct kvm_clock_data clock = {0}; main() local
[all...]
/linux/drivers/crypto/intel/qat/qat_common/
H A Dadf_clock.c1 // SPDX-License-Identifier: GPL-2.0-only
58 delta_us = timespec_to_us(&ts2) - timespec_to_us(&ts1); in measure_clock()
59 } while (delta_us > MEASURE_CLOCK_DELTA_THRESHOLD_US && --tries); in measure_clock()
62 dev_err(&GET_DEV(accel_dev), "Excessive clock measure delay\n"); in measure_clock()
63 return -ETIMEDOUT; in measure_clock()
74 return -EIO; in measure_clock()
77 delta_us = timespec_to_us(&ts4) - timespec_to_us(&ts3); in measure_clock()
78 } while (delta_us > MEASURE_CLOCK_DELTA_THRESHOLD_US && --tries); in measure_clock()
81 dev_err(&GET_DEV(accel_dev), "Excessive clock measure delay\n"); in measure_clock()
82 return -ETIMEDOUT; in measure_clock()
[all …]
/linux/Documentation/devicetree/bindings/mtd/
H A Dlpc32xx-mlc.txt4 - compatible: "nxp,lpc3220-mlc"
5 - reg: Address and size of the controller
6 - interrupts: The NAND interrupt specification
7 - gpios: GPIO specification for NAND write protect
11 Hz, to make them independent of actual clock speed and to provide for good
12 accuracy:)
13 - nxp,tcea_delay: TCEA_DELAY
14 - nxp,busy_delay: BUSY_DELAY
15 - nxp,nand_ta: NAND_TA
16 - nxp,rd_high: RD_HIGH
[all …]
/linux/Documentation/devicetree/bindings/iio/pressure/
H A Dhoneywell,hsc030pa.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
23 pressure-triplet (directly extracted from the part number) or in case it's
27 by the sensor. pmin-pascal and pmax-pascal corespond to the minimum and
30 Please note that in case of an SPI-based sensor, the clock signal should not
34 …-edam.honeywell.com/content/dam/honeywell-edam/sps/siot/en-us/products/sensors/pressure-sensors/bo…
35 …-edam.honeywell.com/content/dam/honeywell-edam/sps/siot/en-us/products/sensors/pressure-sensors/bo…
38 - Petre Rodan <petre.rodan@subdimension.ro>
47 honeywell,transfer-function:
[all …]
/linux/arch/x86/kernel/
H A Dpvclock.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* paravirtual clock -- common code used by kvm/xen
31 do_div(pv_tsc_khz, src->tsc_to_system_mul); in pvclock_tsc_khz()
32 if (src->tsc_shift < 0) in pvclock_tsc_khz()
33 pv_tsc_khz <<= -src->tsc_shift; in pvclock_tsc_khz()
35 pv_tsc_khz >>= src->tsc_shift; in pvclock_tsc_khz()
61 flags = src->flags; in pvclock_read_flags()
78 flags = src->flags; in __pvclock_clocksource_read()
82 src->flags &= ~PVCLOCK_GUEST_STOPPED; in __pvclock_clocksource_read()
94 * does not sacrifice accuracy. in __pvclock_clocksource_read()
[all …]
/linux/tools/perf/Documentation/
H A Dperf-stat.txt1 perf-stat(1)
5 ----
6 perf-stat - Run a command and gather performance counter statistics
9 ---
[all...]
/linux/arch/arm/boot/dts/allwinner/
H A Dsun8i-v3s.dtsi5 * This file is dual-licensed: you can use it either under the terms
44 #include <dt-bindings/interrupt-controller/arm-gic.h>
45 #include <dt-bindings/clock/sun6i-rtc.h>
46 #include <dt-bindings/clock/sun8i-v3s-ccu.h>
47 #include <dt-bindings/reset/sun8i-v3s-ccu.h>
48 #include <dt-bindings/clock/sun8i-de2.h>
51 #address-cells = <1>;
52 #size-cells = <1>;
53 interrupt-parent = <&gic>;
56 #address-cells = <1>;
[all …]
/linux/Documentation/core-api/
H A Dtimekeeping.rst10 ------------------------------
13 that return time for different clock references:
56 clocksource without (NTP) adjustments for clock drift. This is
60 -----------------------------------------
92 Return a coarse-grained version of the time as a scalar
93 time64_t. This avoids accessing the clock hardware and rounds
98 -------------------------
117 These are quicker than the non-coarse versions, but less accurate,
125 in a fast path and one still expects better than second accuracy,
127 Skipping the hardware clock access saves around 100 CPU cycles
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