Searched +full:clmul +full:- +full:fix +full:- +full:loop +full:- +full:end +full:- +full:condition (Results 1 – 3 of 3) sorted by relevance
| /freebsd/sys/contrib/device-tree/Bindings/riscv/ |
| H A D | extensions.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V ISA extensions
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 RISC-V has a large number of extensions, some of which are "standard"
16 extensions, meaning they are ratified by RISC-V International, and others
36 Identifies the specific RISC-V instruction set architecture
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| /freebsd/contrib/xz/ |
| H A D | ChangeLog | 3 Date: 2025-04-03 14:34:43 +0300
7 src/liblzma/Makefile.am | 2 +-
8 src/liblzma/api/lzma/version.h | 2 +-
9 2 files changed, 2 insertions(+), 2 deletions(-)
13 Date: 2025-04-03 14:34:43 +0300
22 Date: 2025-04-03 14:34:43 +0300
32 for OSS-Fuzz.").
34 tests/ossfuzz/fuzz_common.h | 31 ++++++++++++++++++++++++-------
35 1 file changed, 24 insertions(+), 7 deletions(-)
39 Date: 2025-04-03 14:34:43 +0300
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 1 //===-- RISCVISelLowering.cpp - RISC-V DAG Lowering Implementation ------
7270 emitFlushICache(SelectionDAG & DAG,SDValue InChain,SDValue Start,SDValue End,SDValue Flags,SDLoc DL) const emitFlushICache() argument
11330 ISD::CondCode Condition = cast<CondCodeSDNode>(Op.getOperand(2))->get(); lowerVPSetCCMaskOp() local
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