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/linux/Documentation/devicetree/bindings/clock/ti/
H A Dti,clksel.yaml4 $id: http://devicetree.org/schemas/clock/ti/ti,clksel.yaml#
7 title: TI clksel clock
13 The TI CLKSEL clocks consist of consist of input clock mux bits, and in some
18 const: ti,clksel
22 description: The CLKSEL register range
34 description: The CLKSEL register and bit offset
47 compatible = "ti,clksel";
/linux/drivers/clk/rockchip/
H A Dclk-cpu.c105 const struct rockchip_cpuclk_clksel *clksel = &rate->divs[i]; in rockchip_cpuclk_set_dividers() local
107 if (!clksel->reg) in rockchip_cpuclk_set_dividers()
111 __func__, clksel->reg, clksel->val); in rockchip_cpuclk_set_dividers()
112 writel(clksel->val, cpuclk->reg_base + clksel->reg); in rockchip_cpuclk_set_dividers()
123 const struct rockchip_cpuclk_clksel *clksel = &rate->pre_muxs[i]; in rockchip_cpuclk_set_pre_muxs() local
125 if (!clksel->reg) in rockchip_cpuclk_set_pre_muxs()
129 __func__, clksel->reg, clksel->val); in rockchip_cpuclk_set_pre_muxs()
130 writel(clksel->val, cpuclk->reg_base + clksel->reg); in rockchip_cpuclk_set_pre_muxs()
141 const struct rockchip_cpuclk_clksel *clksel = &rate->post_muxs[i]; in rockchip_cpuclk_set_post_muxs() local
143 if (!clksel->reg) in rockchip_cpuclk_set_post_muxs()
[all …]
/linux/drivers/clk/
H A Dclk-milbeaut.c17 #define CLKSEL(n) (((n) - 1) * 4 + M10V_CLKSEL1) macro
254 {"emmc", M10V_PLL11, CLKSEL(1), 28, 3, emmcclk_table, 0,
256 {"mclk400", M10V_PLL1DIV2, CLKSEL(10), 7, 3, mclk400_table, 0, -1},
257 {"mclk200", M10V_PLL1DIV2, CLKSEL(10), 3, 4, mclk200_table, 0, -1},
258 {"aclk400", M10V_PLL1DIV2, CLKSEL(10), 0, 3, aclk400_table, 0, -1},
259 {"aclk300", M10V_PLL2DIV2, CLKSEL(12), 0, 2, aclk300_table, 0, -1},
260 {"aclk", M10V_PLL1DIV2, CLKSEL(9), 20, 4, aclk_table, 0, M10V_ACLK_ID},
261 {"aclkexs", M10V_PLL1DIV2, CLKSEL(9), 16, 4, aclkexs_table, 0, -1},
262 {"hclk", M10V_PLL1DIV2, CLKSEL(9), 7, 5, hclk_table, 0, M10V_HCLK_ID},
263 {"hclkbmh", M10V_PLL1DIV2, CLKSEL(9), 12, 4, hclkbmh_table, 0, -1},
[all …]
H A Dclk-qoriq.c60 struct clockgen_sourceinfo clksel[NUM_MUX_PARENTS]; member
853 u32 clksel; in mux_set_parent() local
858 clksel = hwc->parent_to_clksel[idx]; in mux_set_parent()
859 cg_out(hwc->cg, (clksel << CLKSEL_SHIFT) & CLKSEL_MASK, hwc->reg); in mux_set_parent()
867 u32 clksel; in mux_get_parent() local
870 clksel = (cg_in(hwc->cg, hwc->reg) & CLKSEL_MASK) >> CLKSEL_SHIFT; in mux_get_parent()
872 ret = hwc->clksel_to_parent[clksel]; in mux_get_parent()
874 pr_err("%s: mux at %p has bad clksel\n", __func__, hwc->reg); in mux_get_parent()
901 if (!(hwc->info->clksel[idx].flags & CLKSEL_VALID)) in get_pll_div()
904 pll = hwc->info->clksel[idx].pll; in get_pll_div()
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Domap36xx-omap3430es2plus-clocks.dtsi9 compatible = "ti,clksel";
25 compatible = "ti,clksel";
56 compatible = "ti,clksel";
88 compatible = "ti,clksel";
176 compatible = "ti,clksel";
199 compatible = "ti,clksel";
H A Domap34xx-omap36xx-clocks.dtsi17 compatible = "ti,clksel";
66 compatible = "ti,clksel";
107 compatible = "ti,clksel";
163 compatible = "ti,clksel";
232 compatible = "ti,clksel";
257 compatible = "ti,clksel";
H A Domap3430es1-clocks.dtsi50 compatible = "ti,clksel";
82 compatible = "ti,clksel";
123 compatible = "ti,clksel";
177 compatible = "ti,clksel";
H A Domap36xx-am35xx-omap3430es2plus-clocks.dtsi138 compatible = "ti,clksel";
154 compatible = "ti,clksel";
170 compatible = "ti,clksel";
186 compatible = "ti,clksel";
H A Domap3xxx-clocks.dtsi83 compatible = "ti,clksel";
122 compatible = "ti,clksel";
262 compatible = "ti,clksel";
434 compatible = "ti,clksel";
477 compatible = "ti,clksel";
611 compatible = "ti,clksel";
676 compatible = "ti,clksel";
721 compatible = "ti,clksel";
748 compatible = "ti,clksel";
929 compatible = "ti,clksel";
[all …]
H A Dam35xx-clocks.dtsi66 compatible = "ti,clksel";
102 compatible = "ti,clksel";
H A Dam33xx-clocks.dtsi108 compatible = "ti,clksel";
567 compatible = "ti,clksel";
573 gfx_fclk_clksel_ck: clock-gfx-fclk-clksel@1 {
592 compatible = "ti,clksel";
H A Domap36xx-clocks.dtsi62 compatible = "ti,clksel";
H A Ddra76x.dtsi89 compatible = "ti,clksel";
/linux/drivers/clocksource/
H A Dtimer-cadence-ttc.c488 int clksel, ret; in ttc_timer_probe() local
516 clksel = readl_relaxed(timer_baseaddr + TTC_CLK_CNTRL_OFFSET); in ttc_timer_probe()
517 clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK); in ttc_timer_probe()
518 clk_cs = of_clk_get(timer, clksel); in ttc_timer_probe()
524 clksel = readl_relaxed(timer_baseaddr + 4 + TTC_CLK_CNTRL_OFFSET); in ttc_timer_probe()
525 clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK); in ttc_timer_probe()
526 clk_ce = of_clk_get(timer, clksel); in ttc_timer_probe()
/linux/arch/arm/mach-imx/
H A Dmach-imx6q.c85 u32 clksel; in imx6q_1588_init() local
118 clksel = clk_is_match(ptp_clk, enet_ref) ? in imx6q_1588_init()
125 clksel); in imx6q_1588_init()
/linux/drivers/clk/ti/
H A Dclk.c329 if (of_device_is_compatible(node->parent, "ti,clksel")) { in ti_clk_get_reg_addr()
332 pr_err("%pOFn parent clksel must have reg[%d]!\n", node, index); in ti_clk_get_reg_addr()
340 /* Legacy clksel with no reg and a possible ti,bit-shift property */ in ti_clk_get_reg_addr()
348 /* Updated clksel clock with a proper reg property */ in ti_clk_get_reg_addr()
370 * dropped once all the composite clocks use a clksel node with a
H A Dmux.c29 * numeric. e.g. sys_clkin_ck's clksel field is 3 bits wide, but ranges in ti_clk_mux_get_parent()
/linux/drivers/mmc/host/
H A Ddw_mmc-exynos.h19 /* CLKSEL register defines */
/linux/drivers/gpu/drm/renesas/rcar-du/
H A Drcar_lvds.c138 u32 clksel; member
143 u32 clksel, bool dot_clock_only) in rcar_lvds_d3_e3_pll_calc() argument
251 pll->clksel = clksel; in rcar_lvds_d3_e3_pll_calc()
285 lvdpllcr = LVDPLLCR_PLLON | pll.clksel | LVDPLLCR_CLKOUT in rcar_lvds_pll_setup_d3_e3()
/linux/drivers/net/wireless/mediatek/mt76/mt76x0/
H A Dphy.h71 u8 pllR28_b3b2; /* clksel option */
/linux/Documentation/devicetree/bindings/iio/adc/
H A Dti,ads131e08.yaml36 Note: clock source is selected using CLKSEL pin.
/linux/drivers/pwm/
H A Dpwm-imx1.c84 * both the prescaler (/1 .. /128) and then by CLKSEL in pwm_imx1_config()
/linux/sound/soc/codecs/
H A Dwm8983.h247 #define WM8983_CLKSEL 0x0100 /* CLKSEL */
248 #define WM8983_CLKSEL_MASK 0x0100 /* CLKSEL */
249 #define WM8983_CLKSEL_SHIFT 8 /* CLKSEL */
250 #define WM8983_CLKSEL_WIDTH 1 /* CLKSEL */
H A Dwm8985.h242 #define WM8985_CLKSEL 0x0100 /* CLKSEL */
243 #define WM8985_CLKSEL_MASK 0x0100 /* CLKSEL */
244 #define WM8985_CLKSEL_SHIFT 8 /* CLKSEL */
245 #define WM8985_CLKSEL_WIDTH 1 /* CLKSEL */
/linux/include/linux/clk/
H A Dti.h160 * @clksel_reg: for clksel clks, register va containing src/divisor select

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