Home
last modified time | relevance | path

Searched full:clk_m (Results 1 – 19 of 19) sorted by relevance

/linux/drivers/clk/tegra/
H A Dclk-tegra-periph.c269 "clk_m"};
285 "pll_p", "pll_c", "pll_m", "clk_m"
293 "pll_p", "pll_c", "clk_32k", "clk_m"
298 "pll_a_out0", "pll_c", "pll_p", "clk_m"
303 "pll_p", "pll_c2", "pll_c", "pll_c3", "pll_m", "clk_m"
310 "pll_p", "clk_m"
317 "pll_p", "clk_m"
324 "pll_c2", "pll_c", "pll_c3", "pll_p", "pll_a1", "clk_m"
332 "pll_c4_out1", "pll_c", "pll_c4_out2", "pll_p", "clk_m",
347 "clk_m", "pll_c", "pll_p", "pll_a_out0"
[all …]
H A Dclk-tegra-super-gen4.c45 static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4",
49 static const char *cclk_g_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
55 static const char *cclk_lp_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
69 static const char *sclk_parents_gen5[] = { "clk_m", "pll_c_out1", "pll_c4_out3",
73 static const char *cclk_g_parents_gen5[] = { "clk_m", "unused", "clk_32k", "unused",
79 static const char *cclk_lp_parents_gen5[] = { "clk_m", "unused", "clk_32k", "unused",
H A Dclk-tegra-fixed.c76 clk = clk_register_fixed_factor(NULL, "clk_m", "osc", in tegra_osc_clk_init()
H A Dclk-tegra20-emc.c36 "pll_m", "pll_c", "pll_p", "clk_m",
H A Dclk-sdmmc-mux.c30 "pll_p", "pll_c4_out2", "pll_c4_out0", "pll_c4_out1", "clk_m"
H A Dclk-tegra210-emc.c47 "pll_m", "pll_c", "pll_p", "clk_m", "pll_m_ud", "pll_mb_ud",
H A Dclk-tegra124.c935 { .con_id = "clk_m", .dt_id = TEGRA124_CLK_CLK_M },
1004 "pll_d2_out0", "clk_m",
1008 "clk_m", "sor0_pad_clkout",
1253 /* switch coresite to clk_m, save off original source */ in tegra124_cpu_clock_suspend()
H A Dclk-tegra124-emc.c42 "pll_m", "pll_c", "pll_p", "clk_m", "pll_m_ud",
H A Dclk-tegra210.c2561 { .con_id = "clk_m", .dt_id = TEGRA210_CLK_CLK_M },
2633 "clk_m"
3021 "pll_p", "pll_d_out0", "pll_d2_out0", "clk_m",
3083 "pll_p", "pll_c2", "pll_c", "pll_c3", "pll_re_out1", "pll_a1", "clk_m", "pll_c4_out0"
3513 /* switch coresite to clk_m, save off original source */ in tegra210_cpu_clock_suspend()
/linux/Documentation/devicetree/bindings/usb/
H A Dnvidia,tegra186-xusb.yaml56 - const: clk_m
156 "pll_u_480m", "clk_m", "pll_e";
H A Dnvidia,tegra194-xusb.yaml56 - const: clk_m
159 "xusb_fs_src", "pll_u_480m", "clk_m",
H A Dnvidia,tegra124-xusb.yaml70 - const: clk_m
183 "clk_m", "pll_e";
H A Dnvidia,tegra234-xusb.yaml86 - const: clk_m
171 "xusb_fs_src", "pll_u_480m", "clk_m",
/linux/drivers/video/fbdev/
H A Dimsttfb.c426 __u32 clk_m, clk_n, clk_p; in getclkMHz() local
428 clk_m = par->init.pclk_m; in getclkMHz()
432 return 20 * (clk_m + 1) / ((clk_n + 1) * (clk_p ? 2 * clk_p : 1)); in getclkMHz()
438 __u32 clk_m, clk_n, x, stage, spilled; in setclkMHz() local
440 clk_m = clk_n = 0; in setclkMHz()
445 clk_m++; in setclkMHz()
451 x = 20 * (clk_m + 1) / (clk_n + 1); in setclkMHz()
462 par->init.pclk_m = clk_m; in setclkMHz()
/linux/drivers/usb/host/
H A Dxhci-tegra.c289 struct clk *clk_m; member
453 /* Reparent to CLK_M */ in tegra_xusb_set_ss_clk()
454 err = clk_set_parent(clk, tegra->clk_m); in tegra_xusb_set_ss_clk()
1709 tegra->clk_m = devm_clk_get(&pdev->dev, "clk_m"); in tegra_xusb_probe()
1710 if (IS_ERR(tegra->clk_m)) { in tegra_xusb_probe()
1711 err = PTR_ERR(tegra->clk_m); in tegra_xusb_probe()
1712 dev_err(&pdev->dev, "failed to get clk_m: %d\n", err); in tegra_xusb_probe()
/linux/arch/arm/mach-tegra/
H A Dsleep-tegra30.S682 /* switch the clock source of mselect to be CLK_M */
734 * Set IRQ burst clock source to clk_m; bits 10:8=0
/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra132.dtsi682 "pll_u_480m", "clk_m", "pll_e";
H A Dtegra210.dtsi1106 "pll_u_480m", "clk_m", "pll_e";
/linux/arch/arm/boot/dts/nvidia/
H A Dtegra124.dtsi824 "pll_u_480m", "clk_m", "pll_e";