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/linux/drivers/clk/
H A Dclk-loongson2.c59 #define CLK_DIV(_id, _name, _pname, _offset, _dshift, _dwidth) \ macro
148 CLK_DIV(LS2K0300_CLK_NODE_DIV, "clk_node_div", "pll_node", 0x00, 24, 7),
149 CLK_DIV(LS2K0300_CLK_GMAC_DIV, "clk_gmac_div", "pll_node", 0x04, 0, 7),
150 CLK_DIV(LS2K0300_CLK_I2S_DIV, "clk_i2s_div", "pll_node", 0x04, 8, 7),
159 CLK_DIV(LS2K0300_CLK_DDR_DIV, "clk_ddr_div", "pll_ddr", 0x08, 24, 7),
160 CLK_DIV(LS2K0300_CLK_NET_DIV, "clk_net_div", "pll_ddr", 0x0c, 0, 7),
161 CLK_DIV(LS2K0300_CLK_DEV_DIV, "clk_dev_div", "pll_ddr", 0x0c, 8, 7),
167 CLK_DIV(LS2K0300_CLK_PIX_DIV, "clk_pix_div", "pll_pix", 0x10, 24, 7),
168 CLK_DIV(LS2K0300_CLK_GMACBP_DIV, "clk_gmacbp_div", "pll_pix", 0x14, 0, 7),
174 CLK_DIV(LS2K0300_CLK_SDIO_SCALE, "clk_sdio_scale", "clk_dev_gate", 0x20, 24, 4),
[all …]
H A Dclk-versaclock3.c605 static struct vc3_hw_data clk_div[5]; variable
609 { .hw = &clk_div[VC3_DIV2].hw }
811 static struct vc3_hw_data clk_div[] = { variable
914 &clk_div[VC3_DIV5].hw,
915 &clk_div[VC3_DIV4].hw
929 &clk_div[VC3_DIV5].hw,
930 &clk_div[VC3_DIV4].hw
945 &clk_div[VC3_DIV2].hw,
946 &clk_div[VC3_DIV4].hw
961 &clk_div[VC3_DIV1].hw,
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H A Dclk-bm1880.c183 #define CLK_DIV(_id, _name, _parent, _reg, _shift, _width, _initval, \ macro
372 CLK_DIV(BM1880_CLK_DIV_0_RV, "clk_div_0_rv", &bm1880_pll_clks[1].hw,
374 CLK_DIV(BM1880_CLK_DIV_1_RV, "clk_div_1_rv", &bm1880_pll_clks[2].hw,
376 CLK_DIV(BM1880_CLK_DIV_UART_500M, "clk_div_uart_500m", &bm1880_pll_clks[2].hw,
378 CLK_DIV(BM1880_CLK_DIV_0_AXI1, "clk_div_0_axi1", &bm1880_pll_clks[0].hw,
381 CLK_DIV(BM1880_CLK_DIV_1_AXI1, "clk_div_1_axi1", &bm1880_pll_clks[2].hw,
384 CLK_DIV(BM1880_CLK_DIV_0_AXI6, "clk_div_0_axi6", &bm1880_pll_clks[2].hw,
387 CLK_DIV(BM1880_CLK_DIV_1_AXI6, "clk_div_1_axi6", &bm1880_pll_clks[0].hw,
390 CLK_DIV(BM1880_CLK_DIV_12M_USB, "clk_div_12m_usb", &bm1880_pll_clks[2].hw,
/linux/drivers/pwm/
H A Dpwm-mtk-disp.c73 u32 clk_div, period, high_width, value; in mtk_disp_pwm_apply() local
108 * Find period, high_width and clk_div to suit duty_ns and period_ns. in mtk_disp_pwm_apply()
111 * period_ns = 10^9 * (clk_div + 1) * (period + 1) / PWM_CLK_RATE in mtk_disp_pwm_apply()
112 * duty_ns = 10^9 * (clk_div + 1) * high_width / PWM_CLK_RATE in mtk_disp_pwm_apply()
114 * period = (PWM_CLK_RATE * period_ns) / (10^9 * (clk_div + 1)) - 1 in mtk_disp_pwm_apply()
115 * high_width = (PWM_CLK_RATE * duty_ns) / (10^9 * (clk_div + 1)) in mtk_disp_pwm_apply()
118 clk_div = mul_u64_u64_div_u64(state->period, rate, NSEC_PER_SEC) >> in mtk_disp_pwm_apply()
120 if (clk_div > PWM_CLKDIV_MAX) { in mtk_disp_pwm_apply()
128 div = NSEC_PER_SEC * (clk_div + 1); in mtk_disp_pwm_apply()
151 clk_div << PWM_CLKDIV_SHIFT); in mtk_disp_pwm_apply()
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H A Dpwm-crc.c42 int clk_div; in crc_pwm_calc_clk_div() local
44 clk_div = PWM_BASE_CLK_MHZ * period_ns / (256 * NSEC_PER_USEC); in crc_pwm_calc_clk_div()
45 /* clk_div 1 - 128, maps to register values 0-127 */ in crc_pwm_calc_clk_div()
46 if (clk_div > 0) in crc_pwm_calc_clk_div()
47 clk_div--; in crc_pwm_calc_clk_div()
49 return clk_div; in crc_pwm_calc_clk_div()
100 int clk_div = crc_pwm_calc_clk_div(state->period); in crc_pwm_apply() local
104 clk_div | pwm_output_enable); in crc_pwm_apply()
127 unsigned int clk_div, clk_div_reg, duty_cycle_reg; in crc_pwm_get_state() local
142 clk_div = (clk_div_reg & ~PWM_OUTPUT_ENABLE) + 1; in crc_pwm_get_state()
[all …]
/linux/drivers/clk/mxs/
H A Dclk-div.c12 * struct clk_div - mxs integer divider clock
21 struct clk_div { struct
28 static inline struct clk_div *to_clk_div(struct clk_hw *hw) in to_clk_div() argument
32 return container_of(divider, struct clk_div, divider); in to_clk_div()
38 struct clk_div *div = to_clk_div(hw); in clk_div_recalc_rate()
46 struct clk_div *div = to_clk_div(hw); in clk_div_determine_rate()
54 struct clk_div *div = to_clk_div(hw); in clk_div_set_rate()
73 struct clk_div *div; in mxs_clk_div()
/linux/drivers/net/ethernet/xilinx/
H A Dxilinx_axienet_mdio.c179 u32 clk_div; in axienet_mdio_enable() local
215 /* clk_div can be calculated by deriving it from the equation: in axienet_mdio_enable()
216 * fMDIO = fHOST / ((1 + clk_div) * 2) in axienet_mdio_enable()
219 * fHOST / ((1 + clk_div) * 2) <= 2500000 in axienet_mdio_enable()
222 * 1 / ((1 + clk_div) * 2) <= (2500000 / fHOST) in axienet_mdio_enable()
225 * 1 / (1 + clk_div) <= ((2500000 * 2) / fHOST) in axienet_mdio_enable()
228 * 1 / (1 + clk_div) <= (5000000 / fHOST) in axienet_mdio_enable()
231 * (1 + clk_div) >= (fHOST / 5000000) in axienet_mdio_enable()
234 * clk_div >= (fHOST / 5000000) - 1 in axienet_mdio_enable()
240 clk_div = (host_clock / (mdio_freq * 2)) - 1; in axienet_mdio_enable()
[all …]
H A Dll_temac_mdio.c70 int clk_div; in temac_mdio_setup() local
82 clk_div = 0x3f; /* worst-case default setting */ in temac_mdio_setup()
84 clk_div = bus_hz / (2500 * 1000 * 2) - 1; in temac_mdio_setup()
85 if (clk_div < 1) in temac_mdio_setup()
86 clk_div = 1; in temac_mdio_setup()
87 if (clk_div > 0x3f) in temac_mdio_setup()
88 clk_div = 0x3f; in temac_mdio_setup()
94 temac_indirect_out32(lp, XTE_MC_OFFSET, 1 << 6 | clk_div); in temac_mdio_setup()
/linux/arch/mips/ath25/
H A Dar2315.c208 unsigned int clk_div; in ar2315_sys_clk() local
221 clk_div = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_CLKM_DIV); in ar2315_sys_clk()
222 clk_div = pllc_divide_table[clk_div]; in ar2315_sys_clk()
225 clk_div = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_CLKC_DIV); in ar2315_sys_clk()
226 clk_div = pllc_divide_table[clk_div]; in ar2315_sys_clk()
230 clk_div = 1; in ar2315_sys_clk()
237 return pllc_out / (clk_div * cpu_div); in ar2315_sys_clk()
/linux/include/linux/dma/
H A Dqcom-gpi-dma.h26 * @clk_div: source clock divider
43 u32 clk_div; member
61 * @clk_div: source clock divider
77 u16 clk_div; member
/linux/drivers/spi/
H A Dspi-hisi-kunpeng.c117 u16 clk_div; /* baud rate divider */ member
119 /* clk_div = (1 + div_post) * div_pre */
280 if (chip->clk_div % chip->div_pre == 0) in __hisi_calc_div_reg()
286 if (chip->div_pre > chip->clk_div) in __hisi_calc_div_reg()
287 chip->div_pre = chip->clk_div; in __hisi_calc_div_reg()
289 chip->div_post = (chip->clk_div / chip->div_pre) - 1; in __hisi_calc_div_reg()
298 chip->clk_div = DIV_ROUND_UP(host->max_speed_hz, speed_hz) + 1; in hisi_calc_effective_speed()
299 chip->clk_div &= 0xfffe; in hisi_calc_effective_speed()
300 if (chip->clk_div > CLK_DIV_MAX) in hisi_calc_effective_speed()
301 chip->clk_div = CLK_DIV_MAX; in hisi_calc_effective_speed()
[all …]
H A Dspi-ti-qspi.c173 int clk_div; in ti_qspi_setup_clk() local
177 clk_div = DIV_ROUND_UP(clk_rate, speed_hz) - 1; in ti_qspi_setup_clk()
178 clk_div = clamp(clk_div, 0, QSPI_CLK_DIV_MAX); in ti_qspi_setup_clk()
179 dev_dbg(qspi->dev, "hz: %d, clock divider %d\n", speed_hz, clk_div); in ti_qspi_setup_clk()
183 clk_ctrl_new = QSPI_CLK_EN | clk_div; in ti_qspi_setup_clk()
/linux/sound/soc/sti/
H A Duniperif_player.c316 int clk_div; in uni_player_prepare_iec958() local
318 clk_div = player->mclk / runtime->rate; in uni_player_prepare_iec958()
321 if ((clk_div % 128) || (clk_div <= 0)) { in uni_player_prepare_iec958()
322 dev_err(player->dev, "%s: invalid clk_div %d\n", in uni_player_prepare_iec958()
323 __func__, clk_div); in uni_player_prepare_iec958()
398 SET_UNIPERIF_CTRL_DIVIDER(player, clk_div / 128); in uni_player_prepare_iec958()
419 int output_frame_size, slot_width, clk_div; in uni_player_prepare_pcm() local
430 clk_div = player->mclk / runtime->rate; in uni_player_prepare_pcm()
432 * For 32 bits subframe clk_div must be a multiple of 128, in uni_player_prepare_pcm()
435 if ((slot_width == 32) && (clk_div % 128)) { in uni_player_prepare_pcm()
[all …]
/linux/drivers/bus/
H A Dsunxi-rsb.c655 int clk_div, ret; in sunxi_rsb_hw_init() local
682 clk_div = p_clk_freq / rsb->clk_freq / 2; in sunxi_rsb_hw_init()
683 if (!clk_div) in sunxi_rsb_hw_init()
684 clk_div = 1; in sunxi_rsb_hw_init()
685 else if (clk_div > RSB_CCR_MAX_CLK_DIV + 1) in sunxi_rsb_hw_init()
686 clk_div = RSB_CCR_MAX_CLK_DIV + 1; in sunxi_rsb_hw_init()
688 clk_delay = clk_div >> 1; in sunxi_rsb_hw_init()
692 dev_info(dev, "RSB running at %lu Hz\n", p_clk_freq / clk_div / 2); in sunxi_rsb_hw_init()
693 writel(RSB_CCR_SDA_OUT_DELAY(clk_delay) | RSB_CCR_CLK_DIV(clk_div - 1), in sunxi_rsb_hw_init()
/linux/sound/soc/codecs/
H A Dlpass-va-macro.c613 u8 clk_div; in va_dmic_clk_enable() local
651 clk_div = va->dmic_clk_div; in va_dmic_clk_enable()
660 clk_div << CDC_VA_DMIC_CLK_SEL_SHFT); in va_dmic_clk_enable()
665 if (*dmic_clk_div > clk_div) { in va_dmic_clk_enable()
672 clk_div << CDC_VA_DMIC_CLK_SEL_SHFT); in va_dmic_clk_enable()
678 clk_div = *dmic_clk_div; in va_dmic_clk_enable()
681 *dmic_clk_div = clk_div; in va_dmic_clk_enable()
687 clk_div = 0; in va_dmic_clk_enable()
690 clk_div << CDC_VA_DMIC_CLK_SEL_SHFT); in va_dmic_clk_enable()
692 clk_div in va_dmic_clk_enable()
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/linux/drivers/leds/
H A Dleds-bcm6358.c153 u32 clk_div; in bcm6358_leds_probe() local
169 of_property_read_u32(np, "brcm,clk-div", &clk_div); in bcm6358_leds_probe()
170 switch (clk_div) { in bcm6358_leds_probe()
/linux/drivers/rtc/
H A Drtc-s32g.c70 u32 clk_div; member
75 .clk_div = DIV512_32,
204 switch (priv->rtc_data->clk_div) { in rtc_clk_src_setup()
314 priv->rtc_hz = DIV_ROUND_UP(rtc_hz, priv->rtc_data->clk_div); in s32g_rtc_probe()
/linux/drivers/mmc/host/
H A Dtifm_sd.c98 unsigned int clk_div; member
595 ((1000000000UL / host->clk_freq) * host->clk_div); in tifm_sd_set_data_timeout()
827 host->clk_div = clk_div1; in tifm_sd_ios()
833 host->clk_div = clk_div2; in tifm_sd_ios()
839 host->clk_div = 0; in tifm_sd_ios()
841 host->clk_div &= TIFM_MMCSD_CLKMASK; in tifm_sd_ios()
842 writel(host->clk_div in tifm_sd_ios()
883 host->clk_div = 61; in tifm_sd_initialize_host()
886 writel(host->clk_div | TIFM_MMCSD_POWER, in tifm_sd_initialize_host()
905 writel(host->clk_div | TIFM_MMCSD_POWER, in tifm_sd_initialize_host()
/linux/drivers/video/fbdev/omap/
H A Dsossi.c60 int clk_div; member
124 int div = t->clk_div; in calc_rd_timings()
175 int div = t->clk_div; in calc_wr_timings()
258 _set_timing(sossi.clk_div, in set_timing()
317 int div = t->clk_div; in sossi_convert_timings()
348 sossi.clk_div = t->tim[4]; in sossi_set_timings()
/linux/drivers/media/dvb-frontends/
H A Dstv6110.c29 u8 clk_div; member
214 priv->regs[RSTV6110_CTRL2] |= (priv->clk_div << 6); in stv6110_init()
398 reg0[2] |= (config->clk_div << 6); in stv6110_attach()
418 priv->clk_div = config->clk_div; in stv6110_attach()
/linux/drivers/i2c/busses/
H A Di2c-exynos5.c309 * FSCL = IPCLK / ((CLK_DIV + 1) * 16) in exynos5_i2c_set_timing()
310 * T_SCL_LOW = IPCLK * (CLK_DIV + 1) * (N + M) in exynos5_i2c_set_timing()
313 * T_SCL_HIGH = IPCLK * (CLK_DIV + 1) * (N + M) in exynos5_i2c_set_timing()
334 * (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + 2 * FLT_CYCLE in exynos5_i2c_set_timing()
338 * (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + FLT_CYCLE in exynos5_i2c_set_timing()
341 * temp := (CLK_DIV + 1) * (clk_cycle + 2) in exynos5_i2c_set_timing()
345 * (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + in exynos5_i2c_set_timing()
346 * 2 * ((FLT_CYCLE + 3) - (FLT_CYCLE + 3) % (CLK_DIV + 1)) in exynos5_i2c_set_timing()
351 * Constraints: 4 <= temp, 0 <= CLK_DIV < 256, 2 <= clk_cycle <= 510 in exynos5_i2c_set_timing()
/linux/drivers/gpu/drm/renesas/shmobile/
H A Dshmob_drm_crtc.c205 unsigned int clk_div = sdev->config.clk_div; in shmob_drm_crtc_atomic_enable() local
227 if (clk_div) { in shmob_drm_crtc_atomic_enable()
232 lcdc_write(sdev, LDDCKPAT2R, (1 << (clk_div / 2)) - 1); in shmob_drm_crtc_atomic_enable()
234 if (clk_div == 1) in shmob_drm_crtc_atomic_enable()
237 value |= clk_div; in shmob_drm_crtc_atomic_enable()
H A Dshmob_drm_drv.c213 sdev->config.clk_div = pdata->iface.clk_div; in shmob_drm_probe()
273 .clk_div = 5,
/linux/sound/soc/ti/
H A Domap-dmic.c41 int clk_div; member
194 dmic->clk_div = omap_dmic_select_divider(dmic, params_rate(params)); in omap_dmic_dai_hw_params()
195 if (dmic->clk_div < 0) { in omap_dmic_dai_hw_params()
249 ctrl |= OMAP_DMIC_CLK_DIV(dmic->clk_div); in omap_dmic_dai_prepare()
/linux/drivers/media/pci/solo6x10/
H A Dsolo6x10-g723.c55 int clk_div; in solo_g723_config() local
57 clk_div = (solo_dev->clock_mhz * 1000000) in solo_g723_config()
62 | SOLO_AUDIO_CLK_DIV(clk_div)); in solo_g723_config()

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