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Searched +full:clk +full:- +full:phase +full:- +full:sd +full:- +full:hs (Results 1 – 14 of 14) sorted by relevance

/freebsd/sys/contrib/device-tree/src/arm/intel/socfpga/
H A Dsocfpga_arria10_socdk_sdmmc.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2014-2015 Altera Corporation <www.altera.com>
6 /dts-v1/;
11 cap-sd-highspeed;
12 cap-mmc-highspeed;
13 broken-cd;
14 bus-width = <4>;
15 clk-phase-sd-hs = <0>, <135>;
19 sdmmca-ecc@ff8c2c00 {
20 compatible = "altr,socfpga-sdmmc-ecc";
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H A Dsocfpga_arria5.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
16 clock-frequency = <25000000>;
22 broken-cd;
23 bus-width = <4>;
24 cap-mmc-highspeed;
25 cap-sd-highspeed;
26 clk-phase-sd-hs = <0>, <135>;
30 cpu1-start-addr = <0xffd080c4>;
H A Dsocfpga_cyclone5.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 /dts-v1/;
16 clock-frequency = <25000000>;
22 broken-cd;
23 bus-width = <4>;
24 cap-mmc-highspeed;
25 cap-sd-highspeed;
26 clk-phase-sd-hs = <0>, <135>;
30 cpu1-start-addr = <0xffd080c4>;
H A Dsocfpga_cyclone5_mcv.dtsi1 // SPDX-License-Identifier: GPL-2.0+
10 compatible = "altr,socfpga-cyclone5", "altr,socfpga";
19 &mmc0 { /* On-SoM eMMC */
20 bus-width = <8>;
21 clk-phase-sd-hs = <0>, <135>;
H A Dsocfpga_arria10_mercury_aa1.dtsi1 // SPDX-License-Identifier: GPL-2.0
11 compatible = "enclustra,mercury-aa1", "altr,socfpga-arria10", "altr,socfpga";
25 stdout-path = "serial1:115200n8";
30 phy-mode = "rgmii";
31 phy-addr = <0xffffffff>; /* probe for phy addr */
33 max-frame-size = <3800>;
35 phy-handle = <&phy3>;
38 #address-cells = <1>;
39 #size-cells = <0>;
40 compatible = "snps,dwmac-mdio";
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/freebsd/sys/contrib/device-tree/src/arm/aspeed/
H A Daspeed-ast2600-evb.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
4 /dts-v1/;
6 #include "aspeed-g6.dtsi"
7 #include <dt-bindings/gpio/aspeed-gpio.h>
11 compatible = "aspeed,ast2600-evb", "aspeed,ast2600";
26 reserved-memory {
27 #address-cells = <1>;
28 #size-cells = <1>;
34 compatible = "shared-dma-pool";
41 compatible = "shared-dma-pool";
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/freebsd/sys/contrib/device-tree/Bindings/mmc/
H A Darasan,sdhci.txt7 [2] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 [3] Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
9 [4] Documentation/devicetree/bindings/phy/phy-bindings.txt
12 - compatible: Compatibility string. One of:
13 - "arasan,sdhci-8.9a": generic Arasan SDHCI 8.9a PHY
14 - "arasan,sdhci-4.9a": generic Arasan SDHCI 4.9a PHY
15 - "arasan,sdhci-5.1": generic Arasan SDHCI 5.1 PHY
16 - "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1": rk3399 eMMC PHY
17 For this device it is strongly suggested to include arasan,soc-ctl-syscon.
18 - "xlnx,zynqmp-8.9a": ZynqMP SDHCI 8.9a PHY
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H A Darasan,sdhci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schema
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H A Dmmc-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mmc-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
25 "#address-cell
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/freebsd/sys/contrib/device-tree/src/arm64/xilinx/
H A Dzynqmp-sck-kv-g-revB.dts1 // SPDX-License-Identifier: GPL-2.0
5 * (C) Copyright 2020 - 2021, Xilinx, Inc.
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/net/ti-dp83867.h>
12 #include <dt-bindings/phy/phy.h>
13 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
15 /dts-v1/;
18 &i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */
19 #address-cells = <1>;
20 #size-cells = <0>;
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H A Dzynqmp-sck-kv-g-revB.dtso1 // SPDX-License-Identifier: GPL-2.0
5 * (C) Copyright 2020 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/net/ti-dp83867.h>
13 #include <dt-bindings/phy/phy.h>
14 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
16 /dts-v1/;
20 compatible = "xlnx,zynqmp-sk-kv260-rev2",
21 "xlnx,zynqmp-sk-kv260-rev1",
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/freebsd/sys/contrib/device-tree/src/arm64/intel/
H A Dsocfpga_n5x_socdk.dts1 // SPDX-License-Identifier: GPL-2.0
9 compatible = "intel,n5x-socdk", "intel,socfpga-agilex";
19 stdout-path = "serial0:115200n8";
29 sdram_edac: memory-controller@f87f8000 {
30 compatible = "snps,ddrc-3.80a";
38 compatible = "intel,easic-n5x-clkmgr";
43 phy-mode = "rgmii";
44 phy-handle = <&phy0>;
46 max-frame-size = <9000>;
49 #address-cells = <1>;
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H A Dsocfpga_agilex_socdk.dts1 // SPDX-License-Identifier: GPL-2.0
9 compatible = "intel,socfpga-agilex-socdk", "intel,socfpga-agilex";
19 stdout-path = "serial0:115200n8";
23 compatible = "gpio-leds";
53 phy-mode = "rgmii";
54 phy-handle = <&phy0>;
56 max-frame-size = <9000>;
59 #address-cells = <1>;
60 #size-cells = <0>;
61 compatible = "snps,dwmac-mdio";
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/freebsd/sys/contrib/device-tree/src/arm64/altera/
H A Dsocfpga_stratix10_socdk.dts1 // SPDX-License-Identifier: GPL-2.0-only
10 compatible = "altr,socfpga-stratix10-socdk", "altr,socfpga-stratix10";
20 stdout-path = "serial0:115200n8";
24 compatible = "gpio-leds";
25 led-hps0 {
30 led-hps1 {
35 led-hps2 {
47 ref_033v: regulator-v-ref {
48 compatible = "regulator-fixed";
49 regulator-name = "0.33V";
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