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/linux/Documentation/devicetree/bindings/usb/
H A Dbrcm,usb-pinmap.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/brcm,usb-pinmap.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Al Cooper <alcooperx@gmail.com>
15 - const: brcm,usb-pinmap
22 description: Interrupt for signals mirrored to out-gpios.
24 in-gpios:
29 brcm,in-functions:
30 $ref: /schemas/types.yaml#/definitions/string-array
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/linux/Documentation/devicetree/bindings/net/
H A Dintel,ixp4xx-hss.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/intel,ixp4xx-hss.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Linus Walleij <linus.walleij@linaro.org>
20 const: intel,ixp4xx-hss
26 intel,npe-handle:
27 $ref: /schemas/types.yaml#/definitions/phandle-array
30 - description: phandle to the NPE this HSS instance is using
31 - description: the NPE instance number
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/linux/include/linux/gpio/
H A Ddriver.h1 /* SPDX-License-Identifier: GPL-2.0 */
12 #include <linux/pinctrl/pinconf-generic.h>
48 * struct gpio_irq_chip - GPIO interrupt controller
78 * If non-NULL, will be set as the parent of this GPIO interrupt
90 * hardware IRQs correspond to the GPIO index 0..ngpio-1 (see the
98 * HWIRQ, return -EINVAL, but also make sure to fill in @valid_mask and
113 * &gpiochip_populate_parent_fwspec_twocell will be used. A four-cell
260 * a particular driver wants to clear IRQ related registers
270 * bits from 0..(ngpios-1) set to "1" as in valid. The callback can
281 * If not %NULL, holds bitmask of GPIOs which are valid to be included
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H A Dregmap.h1 /* SPDX-License-Identifier: GPL-2.0-only */
12 #define GPIO_REGMAP_ADDR_ZERO ((unsigned int)(-1))
16 * struct gpio_regmap_config - Description of a generic regmap gpio_chip.
24 * @ngpio: Number of GPIOs
25 * @names: (Optional) Array of names for gpios
28 * @reg_clr_base: (Optional) clear register base address
33 * @ngpio_per_reg: Number of GPIOs per register
35 * interrupt-capable
41 * not used by gpio-remap but is provided "as is" to the
44 * The ->reg_mask_xlate translates a given base address and GPIO offset to
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/linux/Documentation/devicetree/bindings/iio/adc/
H A Dmaxim,max34408.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ivan Mikhaylov <fr0st61te@gmail.com>
13 The MAX34408/MAX34409 are two- and four-channel current monitors that are
15 unidirectional current sensor offers precision high-side operation with a
16 low full-scale sense voltage. The devices automatically sequence through
17 two or four channels and collect the current-sense samples and average them
19 user-programmable digital thresholds to indicate overcurrent conditions.
24 https://www.analog.com/media/en/technical-documentation/data-sheets/MAX34408-MAX34409.pdf
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/linux/drivers/input/keyboard/
H A Dtc3589x-keypad.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) ST-Ericsson SA 2010
68 /* bit masks for keyboard interrupt clear*/
73 * struct tc3589x_keypad_platform_data - platform specific keypad data
95 * struct tc_keypad - data structure used by keypad driver
117 struct tc3589x *tc3589x = keypad->tc3589x; in tc3589x_keypad_init_key_hardware()
118 const struct tc3589x_keypad_platform_data *board = keypad->board; in tc3589x_keypad_init_key_hardware()
121 if (board->kcol > TC3589x_MAX_KPCOL || board->krow > TC3589x_MAX_KPROW) in tc3589x_keypad_init_key_hardware()
122 return -EINVAL; in tc3589x_keypad_init_key_hardware()
126 (board->krow << KP_ROW_SHIFT) | board->kcol); in tc3589x_keypad_init_key_hardware()
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/linux/drivers/gpio/
H A Dgpio-stp-xway.c1 // SPDX-License-Identifier: GPL-2.0-only
77 #define xway_stp_w32_mask(m, clear, set, reg) \ argument
78 xway_stp_w32(m, (xway_stp_r32(m, reg) & ~(clear)) | (set), reg)
85 u8 groups; /* we can drive 1-3 groups of 8bit each */
95 * xway_stp_get() - gpio_chip->get - get gpios.
105 return (xway_stp_r32(chip->virt, XWAY_STP_CPU0) & BIT(gpio)); in xway_stp_get()
109 * xway_stp_set() - gpio_chip->set - set gpios.
121 chip->shadow |= BIT(gpio); in xway_stp_set()
123 chip->shadow &= ~BIT(gpio); in xway_stp_set()
124 xway_stp_w32(chip->virt, chip->shadow, XWAY_STP_CPU0); in xway_stp_set()
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H A Dgpio-cs5535.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2007-2009 Andres Salomon <dilinger@collabora.co.uk>
17 #define DRV_NAME "cs5535-gpio"
21 * 31-29,23 : reserved (always mask out)
24 * 22-16 : LPC
44 * design pattern, see Documentation/driver-api/driver-model/design-patterns.rst
55 * The CS5535/CS5536 GPIOs support a number of extra features not defined
63 unsigned long addr = chip->base + 0x80 + reg; in errata_outl()
67 * a write to the high bank GPIO register will clear all in errata_outl()
68 * non-selected bits; the recommended workaround is a in errata_outl()
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H A Dgpio-davinci.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (c) 2006-2007 David Brownell
43 #define BINTEN 0x8 /* GPIO Interrupt Per-Bank Enable Register */
82 /*--------------------------------------------------------------------------*/
95 g = d->regs[bank]; in __davinci_direction()
96 spin_lock_irqsave(&d->lock, flags); in __davinci_direction()
97 temp = readl_relaxed(&g->dir); in __davinci_direction()
100 writel_relaxed(mask, value ? &g->set_data : &g->clr_data); in __davinci_direction()
104 writel_relaxed(temp, &g->dir); in __davinci_direction()
105 spin_unlock_irqrestore(&d->lock, flags); in __davinci_direction()
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H A Dgpio-pxa.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/plat-pxa/gpio.c
15 #include <linux/gpio-pxa.h>
29 * We handle the GPIOs by banks, each bank covers up to 32 GPIOs with
33 * BANK 0 - 0x0000 0x000C 0x0018 0x0024 0x0030 0x003C 0x0048
34 * BANK 1 - 0x0004 0x0010 0x001C 0x0028 0x0034 0x0040 0x004C
35 * BANK 2 - 0x0008 0x0014 0x0020 0x002C 0x0038 0x0044 0x0050
37 * BANK 3 - 0x0100 0x010C 0x0118 0x0124 0x0130 0x013C 0x0148
38 * BANK 4 - 0x0104 0x0110 0x011C 0x0128 0x0134 0x0140 0x014C
39 * BANK 5 - 0x0108 0x0114 0x0120 0x012C 0x0138 0x0144 0x0150
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H A Dgpio-twl4030.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Access to GPIOs on TWL4030/TPS659x0 chips
5 * Copyright (C) 2006-2007 Texas Instruments, Inc.
8 * Code re-arranged and cleaned up by:
30 * The GPIO "subchip" supports 18 GPIOs which can be configured as
37 * There are also two LED pins used sometimes as output-only GPIOs.
52 /* Mask for GPIO registers when aggregated into a 32-bit integer */
66 /*----------------------------------------------------------------------*/
76 /*----------------------------------------------------------------------*/
101 /*----------------------------------------------------------------------*/
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H A Dgpio-ich.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Intel ICH6-10, Series 5 and 6, Atom C2000 (Avoton/Rangeley) GPIO driver
19 * Each chunk of 32 GPIOs is manipulated via its own USE_SELx, IO_SELx, and
34 {0x00, 0x30, 0x40}, /* USE_SEL[1-3] offsets */
35 {0x04, 0x34, 0x44}, /* IO_SEL[1-3] offsets */
36 {0x0c, 0x38, 0x48}, /* LVL[1-3] offsets */
54 #define ICHX_WRITE(val, reg, base_res) outl(val, (reg) + (base_res)->start)
55 #define ICHX_READ(reg, base_res) inl((reg) + (base_res)->start)
91 struct ichx_desc *desc; /* Pointer to chipset-specific description */
97 static int modparam_gpiobase = -1; /* dynamic */
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/linux/drivers/tty/serial/
H A Dsa1100.c1 // SPDX-License-Identifier: GPL-2.0+
15 #include <linux/platform_data/sa11x0-serial.h>
29 /* We've been assigned a range on the "Low-density serial ports" major */
45 #define UART_GET_UTCR0(sport) __raw_readl((sport)->port.membase + UTCR0)
46 #define UART_GET_UTCR1(sport) __raw_readl((sport)->port.membase + UTCR1)
47 #define UART_GET_UTCR2(sport) __raw_readl((sport)->port.membase + UTCR2)
48 #define UART_GET_UTCR3(sport) __raw_readl((sport)->port.membase + UTCR3)
49 #define UART_GET_UTSR0(sport) __raw_readl((sport)->port.membase + UTSR0)
50 #define UART_GET_UTSR1(sport) __raw_readl((sport)->port.membase + UTSR1)
51 #define UART_GET_CHAR(sport) __raw_readl((sport)->port.membase + UTDR)
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H A Dmxs-auart.c1 // SPDX-License-Identifier: GPL-2.0+
9 * Copyright 2014 Oleksij Rempel <linux@rempel-privat.de>
11 * Copyright 2008-2010 Freescale Semiconductor, Inc.
34 #include <linux/dma-mapping.h>
90 #define AUART_LINECTRL_WLEN(v) ((((v) - 5) & 0x3) << 5)
125 * UART will clear this bit at the end of receive execution.
138 * RW. Receive Timeout Counter Value: number of 8-bit-time to wait before
140 * input is idle, then the watchdog counter will decrement each bit-time. Note
141 * 7-bit-time is added to the programmed value, so a value of zero will set
142 * the counter to 7-bit-time, a value of 0x1 gives 15-bit-time and so on. Also
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H A Dcpm_uart.c1 // SPDX-License-Identifier: GPL-2.0+
14 * (C) 2005-2006 MontaVista Software, Inc.
28 #include <linux/dma-mapping.h>
59 cpm_command(port->command, cmd); in cpm_line_cr_cmd()
69 cbd_t __iomem *bdp = pinfo->tx_bd_base; in cpm_uart_tx_empty()
73 if (in_be16(&bdp->cbd_sc) & BD_SC_READY) in cpm_uart_tx_empty()
76 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP) { in cpm_uart_tx_empty()
83 pr_debug("CPM uart[%d]:tx_empty: %d\n", port->line, ret); in cpm_uart_tx_empty()
93 if (pinfo->gpios[GPIO_RTS]) in cpm_uart_set_mctrl()
94 gpiod_set_value(pinfo->gpios[GPIO_RTS], !(mctrl & TIOCM_RTS)); in cpm_uart_set_mctrl()
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H A Dar933x_uart.c1 // SPDX-License-Identifier: GPL-2.0
3 * Atheros AR933X SoC built-in UART driver
31 #include <asm/mach-ath79/ar933x_uart.h>
35 #define DRIVER_NAME "ar933x-uart"
53 struct mctrl_gpios *gpios; member
60 return readl(up->port.membase + offset); in ar933x_uart_read()
66 writel(value, up->port.membase + offset); in ar933x_uart_write()
98 up->ier |= AR933X_UART_INT_TX_EMPTY; in ar933x_uart_start_tx_interrupt()
99 ar933x_uart_write(up, AR933X_UART_INT_EN_REG, up->ier); in ar933x_uart_start_tx_interrupt()
104 up->ier &= ~AR933X_UART_INT_TX_EMPTY; in ar933x_uart_stop_tx_interrupt()
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H A Datmel_serial.c1 // SPDX-License-Identifier: GPL-2.0+
18 #include <linux/clk-provider.h>
24 #include <linux/dma-mapping.h>
62 /* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we
71 /* Use device name ttyS, major 4, minor 64-68. This is the usual serial port
147 struct mctrl_gpios *gpios; member
167 bool hd_start_rx; /* can start RX during half-duplex operation */
197 { .compatible = "atmel,at91rm9200-usar
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H A Dstm32-usart.c1 // SPDX-License-Identifier: GPL-2.0
9 * Inspired by st-asc.c from STMicroelectronics (c)
16 #include <linux/dma-direction.h>
18 #include <linux/dma-mapping.h>
37 #include "stm32-usart.h"
124 val = readl_relaxed(port->membase + reg); in stm32_usart_set_bits()
126 writel_relaxed(val, port->membase + reg); in stm32_usart_set_bits()
133 val = readl_relaxed(port->membase + reg); in stm32_usart_clr_bits()
135 writel_relaxed(val, port->membase + reg); in stm32_usart_clr_bits()
141 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_tx_empty()
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/linux/drivers/pci/controller/dwc/
H A Dpcie-fu740.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2019-2021 SiFive, Inc.
28 #include "pcie-designware.h"
30 #define to_fu740_pcie(x) dev_get_drvdata((x)->dev)
83 gpiod_set_value_cansleep(afp->reset, 0); in fu740_pcie_assert_reset()
85 writel_relaxed(0x0, afp->mgmt_base + PCIEX8MGMT_PERST_N); in fu740_pcie_assert_reset()
91 writel_relaxed(0x1, afp->mgmt_base + PCIEX8MGMT_PERST_N); in fu740_pcie_deassert_reset()
93 gpiod_set_value_cansleep(afp->reset, 1); in fu740_pcie_deassert_reset()
98 gpiod_set_value_cansleep(afp->pwren, 1); in fu740_pcie_power_on()
117 struct device *dev = afp->pci.dev; in fu740_phyregwrite()
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/linux/Documentation/driver-api/
H A Dpps.rst1 .. SPDX-License-Identifier: GPL-2.0
4 PPS - Pulse Per Second
22 ------
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/linux/drivers/pinctrl/starfive/
H A Dpinctrl-starfive-jh7100.c1 // SPDX-License-Identifier: GPL-2.0
26 #include <dt-bindings/pinctrl/pinctrl-starfive-jh7100.h>
29 #include "../pinctrl-utils.h"
33 #define DRIVER_NAME "pinctrl-starfive"
37 * https://github.com/starfive-tech/JH7100_Docs
48 * The following 32-bit registers come in pairs, but only the offset of the
49 * first register is defined. The first controls (interrupts for) GPIO 0-31 and
50 * the second GPIO 32-63.
54 * Interrupt Type. If set to 1 the interrupt is edge-triggered. If set to 0 the
55 * interrupt is level-triggered.
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/linux/arch/arm/mach-pxa/
H A Dmfp-pxa2xx.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-pxa/mfp-pxa2xx.c
7 * The GPIOs on PXA2xx can be configured as one of many alternate
13 #include <linux/gpio-pxa.h>
21 #include "pxa2xx-regs.h"
22 #include "mfp-pxa2xx.h"
23 #include "mfp-pxa27x.h"
32 #define BANK_OFF(n) (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2))
64 return -EINVAL; in __mfp_config_gpio()
66 /* alternate function and direction at run-time */ in __mfp_config_gpio()
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/linux/Documentation/devicetree/bindings/iio/dac/
H A Dadi,ltc2672.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michael Hennerich <michael.hennerich@analog.com>
11 - Kim Seer Paller <kimseer.paller@analog.com>
14 Analog Devices LTC2672 5 channel, 12-/16-Bit, 300mA DAC
15 https://www.analog.com/media/en/technical-documentation/data-sheets/ltc2672.pdf
20 - adi,ltc2672
25 spi-max-frequency:
28 vcc-supply:
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/linux/drivers/leds/trigger/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
18 For more details read Documentation/leds/leds-class.rst.
23 tristate "LED One-shot Trigger"
25 This allows LEDs to blink in one-shot pulses with parameters
27 sporadic events, when there are no clear begin and end trap points,
53 The flash frequency is a hyperbolic function of the 1-minute
88 when using gpios as switches and triggering the needed LEDs
146 When build as a module this driver will be called ledtrig-tty.
156 capacitive touch-buttons, such as e.g. the menu / home / back buttons
162 When build as a module this driver will be called ledtrig-input-events.
/linux/sound/arm/
H A Dpxa2xx-ac97-lib.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Based on sound/arm/pxa2xx-ac97.c and sound/soc/pxa/pxa2xx-ac97.c
22 #include <sound/pxa2xx-lib.h>
24 #include <linux/platform_data/asoc-pxa.h>
26 #include "pxa2xx-ac97-regs.h"
48 int val = -ENODEV; in pxa2xx_ac97_read()
52 return -ENODEV; in pxa2xx_ac97_read()
75 val = -ETIMEDOUT; in pxa2xx_ac97_read()
114 ret = -EIO; in pxa2xx_ac97_write()
132 …writel(readl(ac97_reg_base + GCR) & ( GCR_COLD_RST), ac97_reg_base + GCR); /* clear everything bu… in pxa_ac97_cold_pxa25x()
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