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/linux/Documentation/devicetree/bindings/clock/
H A Dimx7d-clock.yaml39 - const: ckil
62 clocks = <&ckil>, <&osc>;
63 clock-names = "ckil", "osc";
H A Dimx6sll-clock.yaml40 - const: ckil
66 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
67 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
H A Dimx6sx-clock.yaml42 - const: ckil
70 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>, <&anaclk1>, <&anaclk2>;
71 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1", "anaclk1", "anaclk2";
H A Dimx31-clock.yaml21 ckil 2
/linux/drivers/rtc/
H A Drtc-mxc_v2.c49 * To take care of the asynchronous CKIL clock, all writes from the IP domain
50 * will be synchronized to the CKIL domain.
57 /* Wait for 3 CKIL cycles */ in mxc_rtc_sync_lp_locked()
H A Drtc-snvs.c120 /* Wait for 3 CKIL cycles, about 61.0-91.5 µs */ in rtc_write_sync_lp()
/linux/drivers/clk/imx/
H A Dclk-imx35.c79 /* 81 */ gpu2d_gate, ckil, clk_max enumerator
107 clk[ckil] = imx_clk_fixed("ckil", 32768); in _mx35_clocks_init()
H A Dclk-imx6ul.c65 "dummy", "lcdif_pix", "ahb", "ipg", "ipg_per", "ckil", "pll4_audio_div", };
142 hws[IMX6UL_CLK_CKIL] = imx_get_clk_hw_by_name(ccm_node, "ckil"); in imx6ul_clocks_init()
H A Dclk-imx6sx.c61 "lcdif1_pix", "ahb", "ipg", "perclk", "ckil", "pll4_audio_div",
135 hws[IMX6SX_CLK_CKIL] = imx_get_clk_hw_by_name(ccm_node, "ckil"); in imx6sx_clocks_init()
H A Dclk-imx7d.c358 "pll_audio_post_div", "pll_video_post_div", "ckil", };
394 hws[IMX7D_CKIL] = imx_get_clk_hw_by_name(ccm_node, "ckil"); in imx7d_clocks_init()
H A Dclk-imx6sll.c93 hws[IMX6SLL_CLK_CKIL] = imx_get_clk_hw_by_name(ccm_node, "ckil"); in imx6sll_clocks_init()
H A Dclk-imx6sl.c196 hws[IMX6SL_CLK_CKIL] = imx_obtain_fixed_clock_hw("ckil", 0); in imx6sl_clocks_init()
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6ul-prti6g.dts65 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>, <&clock_ksz8081_out>;
66 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1", "enet1_ref_pad";
H A Dimx6qdl-skov-cpu.dtsi241 clocks = <&osc>, <&ckil>, <&ckih1>, <&anaclk1>, <&anaclk2>, <&clk50m_phy>;
242 clock-names = "osc", "ckil", "ckih1", "anaclk1", "anaclk2", "enet_ref_pad";
H A Dimx50.dtsi64 ckil {
H A Dimx51.dtsi50 ckil {
H A Dimx53.dtsi88 ckil {
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mq.dtsi45 ckil: clock-ckil { label
49 clock-output-names = "ckil";
850 clocks = <&ckil>, <&osc_25m>, <&osc_27m>,
853 clock-names = "ckil", "osc_25m", "osc_27m",