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12

/linux/drivers/gpio/
H A Dgpio-imx-scu.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * to control the PIN resources on SCU domain.
16 #include <dt-bindings/firmware/imx/rsrc.h>
19 struct gpio_chip chip; member
36 static int imx_scu_gpio_get(struct gpio_chip *chip, unsigned int offset) in imx_scu_gpio_get() argument
38 struct scu_gpio_priv *priv = gpiochip_get_data(chip); in imx_scu_gpio_get()
42 scoped_guard(mutex, &priv->lock) { in imx_scu_gpio_get()
43 /* to read PIN state via scu api */ in imx_scu_gpio_get()
44 err = imx_sc_misc_get_control(priv->handle, in imx_scu_gpio_get()
48 dev_err(priv->dev, "SCU get failed: %d\n", err); in imx_scu_gpio_get()
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/linux/Documentation/devicetree/bindings/arm/
H A Dairoha,en7581-chip-scu.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/airoha,en7581-chip-scu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Airoha Chip SCU Controller for EN7581 SoC
10 - Lorenzo Bianconi <lorenzo@kernel.org>
13 The airoha chip-scu block provides a configuration interface for clock,
14 io-muxing and other functionalities used by multiple controllers (e.g. clock,
20 - enum:
21 - airoha,en7581-chip-scu
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/linux/drivers/irqchip/
H A Dirq-aspeed-scu-ic.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Aspeed AST24XX, AST25XX, and AST26XX SCU Interrupt Controller
42 struct regmap *scu; member
54 struct irq_chip *chip = irq_desc_get_chip(desc); in aspeed_scu_ic_irq_handler() local
55 unsigned int mask = scu_ic->irq_enable << ASPEED_SCU_IC_STATUS_SHIFT; in aspeed_scu_ic_irq_handler()
57 chained_irq_enter(chip, desc); in aspeed_scu_ic_irq_handler()
60 * The SCU IC has just one register to control its operation and read in aspeed_scu_ic_irq_handler()
69 regmap_read(scu_ic->scu, scu_ic->reg, &sts); in aspeed_scu_ic_irq_handler()
70 enabled = sts & scu_ic->irq_enable; in aspeed_scu_ic_irq_handler()
73 bit = scu_ic->irq_shift; in aspeed_scu_ic_irq_handler()
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/linux/Documentation/devicetree/bindings/thermal/
H A Dairoha,en7581-thermal.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/thermal/airoha,en7581-thermal.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Christian Marangi <ansuelsmth@gmail.com>
14 const: airoha,en7581-thermal
22 airoha,chip-scu:
23 description: phandle to the chip SCU syscon
26 '#thermal-sensor-cells':
30 - compatible
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/linux/include/linux/mfd/
H A Dintel_soc_pmic.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2012-2014 Intel Corporation. All rights reserved.
25 * struct intel_soc_pmic - Intel SoC PMIC data
28 * @irq_chip_data: IRQ chip data for the PMIC itself
29 * @irq_chip_data_pwrbtn: Chained IRQ chip data for the Power Button
30 * @irq_chip_data_tmu: Chained IRQ chip data for the Time Management Unit
31 * @irq_chip_data_bcu: Chained IRQ chip data for the Burst Control Unit
32 * @irq_chip_data_adc: Chained IRQ chip data for the General Purpose ADC
33 * @irq_chip_data_chgr: Chained IRQ chip data for the External Charger
34 * @irq_chip_data_crit: Chained IRQ chip data for the Critical Event Handler
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/linux/Documentation/devicetree/bindings/arm/ux500/
H A Dboards.txt1 ST-Ericsson Ux500 boards
2 ------------------------
5 compatible = "st-ericsson,mop500" (legacy)
6 compatible = "st-ericsson,u8500"
10 soc: represents the system-on-chip and contains the chip
20 compatible = "ste,dbx500-backupram"
22 scu:
23 see binding for arm/arm,scu.yaml
25 interrupt-controller:
26 see binding for interrupt-controller/arm,gic.txt
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/linux/Documentation/devicetree/bindings/mfd/
H A Daspeed,ast2x00-scu.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mfd/aspeed,ast2x00-scu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 In AST2700 SOC which has two soc connection, each soc have its own scu
13 register control, ast2700-scu0 for soc0, ast2700-scu1 for soc1.
16 - Joel Stanley <joel@jms.id.au>
17 - Andrew Jeffery <andrew@aj.id.au>
22 - enum:
23 - aspeed,ast2400-scu
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/linux/arch/arm/boot/dts/arm/
H A Dvexpress-v2p-ca9.dts1 // SPDX-License-Identifier: GPL-2.0
6 * Cortex-A9 MPCore (V2P-CA9)
8 * HBI-0191B
11 /dts-v1/;
12 #include "vexpress-v2m.dtsi"
15 model = "V2P-CA9";
18 compatible = "arm,vexpress,v2p-ca9", "arm,vexpress";
19 interrupt-parent = <&gic>;
20 #address-cells = <1>;
21 #size-cells = <1>;
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H A Darm-realview-pbx-a9.dts23 /dts-v1/;
24 #include "arm-realview-pbx.dtsi"
28 * This is the RealView Platform Baseboard Explore for Cortex-A9
31 model = "ARM RealView Platform Baseboard Explore for Cortex-A9";
35 #address-cells = <1>;
36 #size-cells = <0>;
37 enable-method = "arm,realview-smp";
39 cpu-map {
51 compatible = "arm,cortex-a9";
53 next-level-cache = <&L2>;
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H A Darm-realview-eb-mp.dtsi23 #include <dt-bindings/interrupt-controller/irq.h>
24 #include <dt-bindings/gpio/gpio.h>
25 #include "arm-realview-eb.dtsi"
30 * and Cortex-A9 MPCore.
34 #address-cells = <1>;
35 #size-cells = <1>;
36 compatible = "arm,realview-eb-soc", "simple-bus";
40 /* Primary interrupt controller in the test chip */
41 intc: interrupt-controller@1f000100 {
42 compatible = "arm,eb11mp-gic";
[all …]
H A Dvexpress-v2p-ca5s.dts1 // SPDX-License-Identifier: GPL-2.0
6 * Cortex-A5 MPCore (V2P-CA5s)
8 * HBI-0225B
11 /dts-v1/;
12 #include "vexpress-v2m-rs1.dtsi"
15 model = "V2P-CA5s";
18 compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress";
19 interrupt-parent = <&gic>;
20 #address-cells = <1>;
21 #size-cells = <1>;
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/linux/drivers/mfd/
H A Dintel_soc_pmic_bxtwc.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2015-2017, 2022 Intel Corporation. All rights reserved.
312 return -EINVAL; in regmap_ipc_byte_reg_read()
323 ret = intel_scu_ipc_dev_command(pmic->scu, PMC_PMIC_ACCESS, in regmap_ipc_byte_reg_read()
342 return -EINVAL; in regmap_ipc_byte_reg_write()
354 return intel_scu_ipc_dev_command(pmic->scu, PMC_PMIC_ACCESS, in regmap_ipc_byte_reg_write()
387 ret = regmap_read(pmic->regmap, bxtwc_reg_addr, &val); in val_show()
407 ret = regmap_write(pmic->regmap, bxtwc_reg_addr, val); in val_store()
434 const struct regmap_irq_chip *chip, in bxtwc_add_chained_irq_chip() argument
437 struct device *dev = pmic->dev; in bxtwc_add_chained_irq_chip()
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/linux/Documentation/devicetree/bindings/net/can/
H A Dfsl,flexcan.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 Flexcan CAN controller on Freescale's ARM and PowerPC system-on-a-chip (SOC).
11 - Marc Kleine-Budde <mkl@pengutronix.de>
16 - enum:
17 - fsl,imx95-flexcan
18 - fsl,imx93-flexcan
19 - fsl,imx8qm-flexcan
20 - fsl,imx8mp-flexcan
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/linux/arch/m68k/atari/
H A Dataints.c2 * arch/m68k/atari/ataints.c -- Atari Linux interrupt handling code
5 * Added support for TT interrupts; setup for TT SCU (may someone has
6 * twiddled there and we won't get the right interrupts :-()
8 * Major change: The device-independent code in m68k/ints.c didn't know
9 * about non-autovec ints yet. It hardcoded the number of possible ints to
10 * 7 (IRQ1...IRQ7). But the Atari has lots of non-autovec ints! I made the
16 * 1995-07-16 Lars Brinkhoff <f93labr@dd.chalmers.se>:
27 * 1996-09-03 lars brinkhoff <f93labr@dd.chalmers.se>:
59 * --------------------------------
62 * <asm/atariints.h>): Autovector interrupts are 1..7, then follow ST-MFP,
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H A Dconfig.c40 #include <asm/bootinfo-atari.h>
78 /* ++roman: This is a more elaborate test for an SCC chip, since the plain
81 * resides generate DTACK without the chip, too.
118 * Parse an Atari-specific record in the bootinfo
124 const void *data = record->data; in atari_parse_bootinfo()
126 switch (be16_to_cpu(record->tag)) { in atari_parse_bootinfo()
141 /* Parse the Atari-specific switches= option. */
233 * hardware, we assume that the ST-DMA serves SCSI instead of in config_atari()
238 pr_cont(" STDMA-SCSI"); in config_atari()
265 * The ST-DMA address registers aren't readable in config_atari()
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/linux/arch/arm/mach-rockchip/
H A Dplatsmp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
57 np = dev->of_node; in rockchip_get_core_reset()
92 ret = -1; in pmu_set_power_domain()
122 return -ENXIO; in rockchip_boot_secondary()
128 return -ENXIO; in rockchip_boot_secondary()
159 * rockchip_smp_prepare_sram - populate necessary sram block
160 * Starting cores execute the code residing at the start of the on-chip sram
161 * after power-on. Therefore make sure, this sram region is reserved and
163 * core to the real startup code in ram into the sram-region.
164 * @node: mmio-sram device node
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/linux/drivers/nvmem/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
38 calibration data required for the PCIe or the USB-C PHY.
41 be called nvmem-apple-efuses.
50 and RTC-related settings on a SPMI-attached PMIC present on Apple
54 will be called apple-nvmem-spmi.
57 tristate "Broadcom On-Chip OTP Controller support"
66 will be called nvmem-bcm-ocotp.
86 will be called nvmem-imx-iim.
89 tristate "i.MX 6/7/8 On-Chip OTP Controller support"
93 This is a driver for the On-Chip OTP Controller (OCOTP) available on
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/linux/arch/arm/boot/dts/synaptics/
H A Dberlin2.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
11 #include <dt-bindings/clock/berlin2.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #address-cells = <1>;
18 #size-cells = <1>;
27 #address-cells = <1>;
28 #size-cells = <0>;
29 enable-method = "marvell,berlin-smp";
34 next-level-cache = <&l2>;
38 clock-latency = <100000>;
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H A Dberlin2q.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Copyright (C) 2014 Antoine Ténart <antoine.tenart@free-electrons.com>
6 #include <dt-bindings/clock/berlin2q.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 model = "Marvell Armada 1500 pro (BG2-Q) SoC";
12 #address-cells = <1>;
13 #size-cells = <1>;
21 #address-cells = <1>;
22 #size-cells = <0>;
23 enable-method = "marvell,berlin-smp";
[all …]
H A Dberlin2cd.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Device Tree Include file for Marvell Armada 1500-mini (Berlin BG2CD) SoC
11 #include <dt-bindings/clock/berlin2.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 model = "Marvell Armada 1500-mini (BG2CD) SoC";
17 #address-cells = <1>;
18 #size-cells = <1>;
26 #address-cells = <1>;
27 #size-cells = <0>;
30 compatible = "arm,cortex-a9";
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/linux/drivers/pinctrl/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
80 will be called pinctrl-apple-gpio.
83 bool "Axis ARTPEC-6 pin controller driver"
88 This is the driver for the Axis ARTPEC-6 pin controller. This driver
91 found in Documentation/devicetree/bindings/pinctrl/axis,artpec6-pinctrl.txt
100 functionality. This driver supports the pinmux, push-pull and
129 tristate "X-Powers AXP209 PMIC pinctrl and GPIO Support"
153 The Awinic AW9523/AW9523B is a multi-function I2C GPIO
180 called pinctrl-cy8c95x0.
183 tristate "TI DA850/OMAP-L138/AM18XX pull-up and pull-down groups"
[all …]
/linux/drivers/clk/
H A Dclk-en7523.c1 // SPDX-License-Identifier: GPL-2.0-only
4 #include <linux/clk-provider.h>
10 #include <linux/reset-controller.h>
11 #include <dt-bindings/clock/en7523-clk.h>
12 #include <dt-bindings/reset/airoha,en7581-reset.h>
362 if (!desc->base_bits) in en7523_get_base_rate()
363 return desc->base_value; in en7523_get_base_rate()
365 val >>= desc->base_shift; in en7523_get_base_rate()
366 val &= (1 << desc->base_bits) - 1; in en7523_get_base_rate()
368 if (val >= desc->n_base_values) in en7523_get_base_rate()
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/linux/drivers/thermal/
H A Dairoha_thermal.c1 // SPDX-License-Identifier: GPL-2.0-or-later
14 /* SCU regs */
28 /* period unit calculated in BUS clock * 256 scaling-up */
66 * - Fire BIT(1) when lower than EN7581_COLD_THRE
67 * - Fire BIT(0) and BIT(5) when higher than EN7581_HOT2NORMAL_THRE or
105 * - Fire BIT(1) when lower than EN7581_COLD_THRE
106 * - Fire BIT(0) and BIT(5) when higher than EN7581_HOT2NORMAL_THRE or
156 * - 1 sample
157 * - 2 sample and make average of them
158 * - 4,6,10,16 sample, drop max and min and make average of them
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/linux/drivers/input/keyboard/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
24 board-specific setup logic must also provide a configuration data
38 be called adp5520-keys.
51 module will be called adp5588-keys.
61 module will be called adp5589-keys.
126 Say Y here if you have a PA-RISC machine and want to use an AT or
128 PA-RISC keyboards.
138 built-in keyboard (as opposed to an external keyboard).
152 in the left-hand column will be interpreted as the corresponding key
153 in the right-hand column.
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/linux/arch/m68k/include/asm/
H A Datarihw.h2 ** linux/atarihw.h -- This header defines some macros and pointers for
10 ** 1996-09-13 lars brinkhoff <f93labr@dd.chalmers.se>:
24 #include <asm/bootinfo-atari.h>
65 * Define several Hardware-Chips for indication so that for the ATARI we do
78 ATARIHW_DECLARE(STND_SHIFTER); /* ST-Shifter - no base low ! */
79 ATARIHW_DECLARE(EXTD_SHIFTER); /* STe-Shifter - 24 bit address */
80 ATARIHW_DECLARE(TT_SHIFTER); /* TT-Shifter */
81 ATARIHW_DECLARE(VIDEL_SHIFTER); /* Falcon-Shifter */
84 ATARIHW_DECLARE(PCM_8BIT); /* PCM-Sound in STe-ATARI */
88 ATARIHW_DECLARE(ST_SCSI); /* NCR5380 via ST-DMA (Falcon) */
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