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/linux/drivers/char/xillybus/
H A Dxillybus_core.c102 "Malformed message (skipping): opcode=%d, channel=%03x, dir=%d, bufno=%03x, data=%07x\n", in malformed_message()
120 struct xilly_channel *channel; in xillybus_isr() local
177 channel = ep->channels[msg_channel]; in xillybus_isr()
179 if (msg_dir) { /* Write channel */ in xillybus_isr()
180 if (msg_bufno >= channel->num_wr_buffers) { in xillybus_isr()
184 spin_lock(&channel->wr_spinlock); in xillybus_isr()
185 channel->wr_buffers[msg_bufno]->end_offset = in xillybus_isr()
187 channel->wr_fpga_buf_idx = msg_bufno; in xillybus_isr()
188 channel->wr_empty = 0; in xillybus_isr()
189 channel->wr_sleepy = 0; in xillybus_isr()
[all …]
/linux/drivers/rpmsg/
H A Dqcom_glink_native.c71 * @in_use: To mark if intent is already in use for the channel
97 * @lcids: idr of all channels with a known local channel id
98 * @rcids: idr of all channels with a known remote channel id
139 * struct glink_channel - internal representation of a channel
141 * @ept: rpmsg endpoint this channel is associated with
143 * @refcount: refcount for the channel object
145 * @name: unique channel name/identifier
146 * @lcid: channel id, in local space
147 * @rcid: channel id, in remote space
228 struct glink_channel *channel; in qcom_glink_alloc_channel() local
[all …]
H A Dqcom_glink_trace.h64 TP_PROTO(const char *remote, const char *channel, u16 lcid, u16 rcid, bool tx),
65 TP_ARGS(remote, channel, lcid, rcid, tx),
68 __string(channel, channel)
75 __assign_str(channel);
80 TP_printk("%s remote: %s channel: %s[%u/%u]",
83 __get_str(channel),
92 TP_PROTO(const char *remote, const char *channel, u16 lcid, u16 rcid, bool tx),
93 TP_ARGS(remote, channel, lcid, rcid, tx),
96 __string(channel, channel)
103 __assign_str(channel);
[all …]
/linux/drivers/phy/renesas/
H A Dr8a779f0-ether-serdes.c37 struct r8a779f0_eth_serdes_channel channel[R8A779F0_ETH_SERDES_NUM]; member
60 r8a779f0_eth_serdes_reg_wait(struct r8a779f0_eth_serdes_channel *channel, in r8a779f0_eth_serdes_reg_wait() argument
66 iowrite32(bank, channel->addr + R8A779F0_ETH_SERDES_BANK_SELECT); in r8a779f0_eth_serdes_reg_wait()
68 ret = readl_poll_timeout_atomic(channel->addr + offs, val, in r8a779f0_eth_serdes_reg_wait()
72 dev_dbg(&channel->phy->dev, in r8a779f0_eth_serdes_reg_wait()
74 __func__, channel->index, offs, bank, mask, expected); in r8a779f0_eth_serdes_reg_wait()
82 struct r8a779f0_eth_serdes_channel *channel; in r8a779f0_eth_serdes_common_init_ram() local
86 channel = &dd->channel[i]; in r8a779f0_eth_serdes_common_init_ram()
87 ret = r8a779f0_eth_serdes_reg_wait(channel, 0x026c, 0x180, BIT(0), 0x01); in r8a779f0_eth_serdes_common_init_ram()
98 r8a779f0_eth_serdes_common_setting(struct r8a779f0_eth_serdes_channel *channel) in r8a779f0_eth_serdes_common_setting() argument
[all …]
/linux/drivers/staging/greybus/
H A Dlight.c65 static void gb_lights_channel_free(struct gb_channel *channel);
67 static struct gb_connection *get_conn_from_channel(struct gb_channel *channel) in get_conn_from_channel() argument
69 return channel->light->glights->connection; in get_conn_from_channel()
77 static bool is_channel_flash(struct gb_channel *channel) in is_channel_flash() argument
79 return !!(channel->mode & (GB_CHANNEL_MODE_FLASH | GB_CHANNEL_MODE_TORCH in is_channel_flash()
90 static struct led_classdev *get_channel_cdev(struct gb_channel *channel) in get_channel_cdev() argument
92 return &channel->fled.led_cdev; in get_channel_cdev()
98 struct gb_channel *channel; in get_channel_from_mode() local
102 channel = &light->channels[i]; in get_channel_from_mode()
103 if (channel->mode == mode) in get_channel_from_mode()
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/linux/drivers/ipack/devices/
H A Dipoctal.c48 struct ipoctal_channel channel[NR_CHANNELS]; member
57 return container_of(chan, struct ipoctal, channel[index]); in chan_to_ipoctal()
60 static void ipoctal_reset_channel(struct ipoctal_channel *channel) in ipoctal_reset_channel() argument
62 iowrite8(CR_DISABLE_RX | CR_DISABLE_TX, &channel->regs->w.cr); in ipoctal_reset_channel()
63 channel->rx_enable = 0; in ipoctal_reset_channel()
64 iowrite8(CR_CMD_RESET_RX, &channel->regs->w.cr); in ipoctal_reset_channel()
65 iowrite8(CR_CMD_RESET_TX, &channel->regs->w.cr); in ipoctal_reset_channel()
66 iowrite8(CR_CMD_RESET_ERR_STATUS, &channel->regs->w.cr); in ipoctal_reset_channel()
67 iowrite8(CR_CMD_RESET_MR, &channel->regs->w.cr); in ipoctal_reset_channel()
72 struct ipoctal_channel *channel; in ipoctal_port_activate() local
[all …]
/linux/drivers/most/
H A Dmost_snd.c28 * struct channel - private structure to keep channel specific data
31 * @iface: interface for which the channel belongs to
32 * @cfg: channel configuration
35 * @id: channel index
44 struct channel { struct
152 * get_channel - get pointer to channel
154 * @channel_id: channel ID
156 * This traverses the channel list and returns the channel matching the
159 * Returns pointer to channel on success or NULL otherwise.
161 static struct channel *get_channel(struct most_interface *iface, in get_channel()
[all …]
/linux/drivers/dma/sh/
H A Drz-dmac.c204 static void rz_dmac_ch_writel(struct rz_dmac_chan *channel, unsigned int val, in rz_dmac_ch_writel() argument
208 writel(val, channel->ch_base + offset); in rz_dmac_ch_writel()
210 writel(val, channel->ch_cmn_base + offset); in rz_dmac_ch_writel()
213 static u32 rz_dmac_ch_readl(struct rz_dmac_chan *channel, in rz_dmac_ch_readl() argument
217 return readl(channel->ch_base + offset); in rz_dmac_ch_readl()
219 return readl(channel->ch_cmn_base + offset); in rz_dmac_ch_readl()
227 static void rz_lmdesc_setup(struct rz_dmac_chan *channel, in rz_lmdesc_setup() argument
232 channel->lmdesc.base = lmdesc; in rz_lmdesc_setup()
233 channel->lmdesc.head = lmdesc; in rz_lmdesc_setup()
234 channel->lmdesc.tail = lmdesc; in rz_lmdesc_setup()
[all …]
/linux/drivers/hsi/clients/
H A Dhsi_char.c66 * struct hsc_channel - hsi_char internal channel data
67 * @ch: channel number
68 * @flags: Keeps state of the channel (open/close, reading, writing)
116 static void hsc_add_tail(struct hsc_channel *channel, struct hsi_msg *msg, in hsc_add_tail() argument
121 spin_lock_irqsave(&channel->lock, flags); in hsc_add_tail()
123 spin_unlock_irqrestore(&channel->lock, flags); in hsc_add_tail()
126 static struct hsi_msg *hsc_get_first_msg(struct hsc_channel *channel, in hsc_get_first_msg() argument
132 spin_lock_irqsave(&channel->lock, flags); in hsc_get_first_msg()
140 spin_unlock_irqrestore(&channel->lock, flags); in hsc_get_first_msg()
161 static void hsc_reset_list(struct hsc_channel *channel, struct list_head *l) in hsc_reset_list() argument
[all …]
/linux/Documentation/devicetree/bindings/dma/
H A Dcirrus,ep9301-dma-m2p.yaml30 - description: m2p0 channel registers
31 - description: m2p1 channel registers
32 - description: m2p2 channel registers
33 - description: m2p3 channel registers
34 - description: m2p4 channel registers
35 - description: m2p5 channel registers
36 - description: m2p6 channel registers
37 - description: m2p7 channel registers
38 - description: m2p8 channel registers
39 - description: m2p9 channel registers
[all …]
/linux/drivers/net/ipa/
H A Dgsi.c52 * of data to or from the IPA. A channel is implemented as a ring buffer,
59 * one or more TREs to a channel, the writer (either the IPA or an EE) writes
63 * Each channel has a GSI "event ring" associated with it. An event ring
64 * is implemented very much like a channel ring, but is always directed from
65 * the IPA to an EE. The IPA notifies an EE (such as the AP) about channel
66 * events by adding an entry to the event ring associated with the channel.
69 * to the channel TRE whose completion the event represents.
71 * Each TRE in a channel ring has a set of flags. One flag indicates whether
73 * an interrupt) in the channel's event ring. Other flags allow transfer
76 * to signal completion of channel transfers.
[all …]
/linux/drivers/scsi/qla2xxx/
H A Dqla_devtbl.h8 "QLA2340", "133MHz PCI-X to 2Gb FC, Single Channel", /* 0x100 */
9 "QLA2342", "133MHz PCI-X to 2Gb FC, Dual Channel", /* 0x101 */
10 "QLA2344", "133MHz PCI-X to 2Gb FC, Quad Channel", /* 0x102 */
11 "QCP2342", "cPCI to 2Gb FC, Dual Channel", /* 0x103 */
12 "QSB2340", "SBUS to 2Gb FC, Single Channel", /* 0x104 */
13 "QSB2342", "SBUS to 2Gb FC, Dual Channel", /* 0x105 */
14 "QLA2310", "Sun 66MHz PCI-X to 2Gb FC, Single Channel", /* 0x106 */
15 "QLA2332", "Sun 66MHz PCI-X to 2Gb FC, Single Channel", /* 0x107 */
16 "QCP2332", "Sun cPCI to 2Gb FC, Dual Channel", /* 0x108 */
17 "QCP2340", "cPCI to 2Gb FC, Single Channel", /* 0x109 */
[all …]
/linux/sound/soc/codecs/
H A Dtas5086.c70 #define TAS5086_CHANNEL_VOL(X) (0x08 + (X)) /* Channel 1-6 volume */
537 SOC_DOUBLE_R_TLV("Channel 1/2 Playback Volume",
540 SOC_DOUBLE_R_TLV("Channel 3/4 Playback Volume",
543 SOC_DOUBLE_R_TLV("Channel 5/6 Playback Volume",
567 SOC_DAPM_ENUM("Channel 1 input", tas5086_dapm_input_mux_enum[0]),
568 SOC_DAPM_ENUM("Channel 2 input", tas5086_dapm_input_mux_enum[1]),
569 SOC_DAPM_ENUM("Channel 3 input", tas5086_dapm_input_mux_enum[2]),
570 SOC_DAPM_ENUM("Channel 4 input", tas5086_dapm_input_mux_enum[3]),
571 SOC_DAPM_ENUM("Channel 5 input", tas5086_dapm_input_mux_enum[4]),
572 SOC_DAPM_ENUM("Channel
[all...]
/linux/drivers/net/wwan/iosm/
H A Diosm_ipc_imem_ops.c15 /* Open a packet data online channel between the network layer and CP. */
79 /* Initialize wwan channel */
142 /* return true if channel is ready for use */
144 struct ipc_mem_channel *channel) in ipc_imem_is_channel_active() argument
162 if (channel->state != IMEM_CHANNEL_RESERVED) { in ipc_imem_is_channel_active()
164 "ch[%d]:invalid channel state %d,expected %d", in ipc_imem_is_channel_active()
165 channel->channel_id, channel->state, in ipc_imem_is_channel_active()
174 channel->channel_id, phase); in ipc_imem_is_channel_active()
177 /* Check the full availability of the channel. */ in ipc_imem_is_channel_active()
178 if (channel->state != IMEM_CHANNEL_ACTIVE) { in ipc_imem_is_channel_active()
[all …]
/linux/drivers/hsi/controllers/
H A Domap_ssi_regs.h33 # define SSI_DATAACCEPT(channel) (1 << (channel)) argument
34 # define SSI_DATAAVAILABLE(channel) (1 << ((channel) + 8)) argument
35 # define SSI_DATAOVERRUN(channel) (1 << ((channel) + 16)) argument
40 # define SSI_GDD_LCH(channel) (1 << (channel)) argument
44 # define SSI_WAKE(channel) (1 << (channel)) argument
62 # define SSI_FULL(channel) (1 << (channel)) argument
71 #define SSI_SST_BUFFER_CH_REG(channel) (0x80 + ((channel) * 4)) argument
72 #define SSI_SST_SWAPBUF_CH_REG(channel) (0xc0 + ((channel) * 4)) argument
82 # define SSI_NOTEMPTY(channel) (1 << (channel)) argument
91 #define SSI_SSR_BUFFER_CH_REG(channel) (0x80 + ((channel) * 4)) argument
[all …]
/linux/sound/soc/sprd/
H A Dsprd-mcdt.c57 /* Channel water mark definition */
62 /* DMA channel select definition */
75 /* DMA channel ACK select definition */
78 /* Channel FIFO definition */
128 static void sprd_mcdt_dac_set_watermark(struct sprd_mcdt_dev *mcdt, u8 channel, in sprd_mcdt_dac_set_watermark() argument
131 u32 reg = MCDT_DAC0_WTMK + channel * 4; in sprd_mcdt_dac_set_watermark()
140 static void sprd_mcdt_adc_set_watermark(struct sprd_mcdt_dev *mcdt, u8 channel, in sprd_mcdt_adc_set_watermark() argument
143 u32 reg = MCDT_ADC0_WTMK + channel * 4; in sprd_mcdt_adc_set_watermark()
152 static void sprd_mcdt_dac_dma_enable(struct sprd_mcdt_dev *mcdt, u8 channel, in sprd_mcdt_dac_dma_enable() argument
155 u32 shift = MCDT_DAC_DMA_SHIFT + channel; in sprd_mcdt_dac_dma_enable()
[all …]
/linux/Documentation/sound/designs/
H A Dchannel-mapping-api.rst2 ALSA PCM channel-mapping API
10 The channel mapping API allows user to query the possible channel maps
11 and the current channel map, also optionally to modify the channel map
14 A channel map is an array of position for each PCM channel.
15 Typically, a stereo PCM stream has a channel map of
17 while a 4.0 surround PCM stream has a channel map of
20 The problem, so far, was that we had no standard channel map
21 explicitly, and applications had no way to know which channel
29 was no way to specify this because of lack of channel map
30 specification. These are the main motivations for the new channel
[all …]
/linux/drivers/mailbox/
H A Dmailbox-sti.c30 #define STI_IRQ_SET_OFFSET 0x24 /* Generate a Tx channel interrupt */
33 #define STI_ENA_SET_OFFSET 0x84 /* Enable a channel */
34 #define STI_ENA_CLR_OFFSET 0xa4 /* Disable a channel */
42 * @mbox: Representation of a communication channel controller
51 * A channel an be used for TX or RX
66 * @num_chan: Maximum number of channel per instance
74 * struct sti_channel - STi Mailbox allocated channel information
77 * @instance: Instance number channel resides in
78 * @channel: Channel number pertaining to this container
83 unsigned int channel; member
[all …]
/linux/drivers/gpu/host1x/
H A Dchannel.c3 * Tegra host1x Channel
11 #include "channel.h"
43 struct host1x *host = dev_get_drvdata(job->channel->dev->parent); in host1x_job_submit()
49 struct host1x_channel *host1x_channel_get(struct host1x_channel *channel) in host1x_channel_get() argument
51 kref_get(&channel->refcount); in host1x_channel_get()
53 return channel; in host1x_channel_get()
58 * host1x_channel_get_index() - Attempt to get channel reference by index
60 * @index: Index of channel
62 * If channel number @index is currently allocated, increase its refcount
76 void host1x_channel_stop(struct host1x_channel *channel) in host1x_channel_stop() argument
[all …]
/linux/Documentation/networking/
H A Dppp_generic.rst4 PPP Generic Driver and Channel Interface
26 the services of PPP ``channels``. A PPP channel encapsulates a
28 PPP channel implementation can be arbitrarily complex internally but
31 handle ioctl requests. Currently there are PPP channel
36 natural and straightforward way, by allowing more than one channel to
42 PPP channel API
49 Each channel has to provide two functions to the generic PPP layer,
53 send. The channel has the option of rejecting the frame for
55 and the channel should call the ppp_output_wakeup() function at a
61 program to control aspects of the channel's behaviour. This
[all …]
/linux/drivers/firmware/tegra/
H A Dbpmp.c28 channel_to_ops(struct tegra_bpmp_channel *channel) in channel_to_ops() argument
30 struct tegra_bpmp *bpmp = channel->bpmp; in channel_to_ops()
72 tegra_bpmp_channel_get_thread_index(struct tegra_bpmp_channel *channel) in tegra_bpmp_channel_get_thread_index() argument
74 struct tegra_bpmp *bpmp = channel->bpmp; in tegra_bpmp_channel_get_thread_index()
80 index = channel - channel->bpmp->threaded_channels; in tegra_bpmp_channel_get_thread_index()
95 static bool tegra_bpmp_is_response_ready(struct tegra_bpmp_channel *channel) in tegra_bpmp_is_response_ready() argument
97 const struct tegra_bpmp_ops *ops = channel_to_ops(channel); in tegra_bpmp_is_response_ready()
99 return ops->is_response_ready(channel); in tegra_bpmp_is_response_ready()
102 static bool tegra_bpmp_is_request_ready(struct tegra_bpmp_channel *channel) in tegra_bpmp_is_request_ready() argument
104 const struct tegra_bpmp_ops *ops = channel_to_ops(channel); in tegra_bpmp_is_request_ready()
[all …]
/linux/drivers/gpu/drm/xe/
H A Dxe_hwmon.c143 static int xe_hwmon_pcode_read_power_limit(const struct xe_hwmon *hwmon, u32 attr, int channel, in xe_hwmon_pcode_read_power_limit() argument
151 (channel == CHANNEL_CARD) ? in xe_hwmon_pcode_read_power_limit()
160 channel, val0, val1, ret); in xe_hwmon_pcode_read_power_limit()
178 static int xe_hwmon_pcode_rmw_power_limit(const struct xe_hwmon *hwmon, u32 attr, u8 channel, in xe_hwmon_pcode_rmw_power_limit() argument
186 (channel == CHANNEL_CARD) ? in xe_hwmon_pcode_rmw_power_limit()
195 channel, val0, val1, ret); in xe_hwmon_pcode_rmw_power_limit()
205 (channel == CHANNEL_CARD) ? in xe_hwmon_pcode_rmw_power_limit()
211 channel, val0, val1, ret); in xe_hwmon_pcode_rmw_power_limit()
216 int channel) in xe_hwmon_get_reg() argument
223 if (channel in xe_hwmon_get_reg()
287 xe_hwmon_power_max_read(struct xe_hwmon * hwmon,u32 attr,int channel,long * value) xe_hwmon_power_max_read() argument
331 xe_hwmon_power_max_write(struct xe_hwmon * hwmon,u32 attr,int channel,long value) xe_hwmon_power_max_write() argument
406 xe_hwmon_power_rated_max_read(struct xe_hwmon * hwmon,u32 attr,int channel,long * value) xe_hwmon_power_rated_max_read() argument
451 xe_hwmon_energy_get(struct xe_hwmon * hwmon,int channel,long * energy) xe_hwmon_energy_get() argument
500 int channel = (to_sensor_dev_attr(attr)->index % 2) ? CHANNEL_PKG : CHANNEL_CARD; xe_hwmon_power_max_interval_show() local
556 int channel = (to_sensor_dev_attr(attr)->index % 2) ? CHANNEL_PKG : CHANNEL_CARD; xe_hwmon_power_max_interval_store() local
655 int channel = (index % 2) ? CHANNEL_PKG : CHANNEL_CARD; xe_hwmon_attributes_visible() local
736 xe_hwmon_power_curr_crit_read(struct xe_hwmon * hwmon,int channel,long * value,u32 scale_factor) xe_hwmon_power_curr_crit_read() argument
755 xe_hwmon_power_curr_crit_write(struct xe_hwmon * hwmon,int channel,long value,u32 scale_factor) xe_hwmon_power_curr_crit_write() argument
784 xe_hwmon_get_voltage(struct xe_hwmon * hwmon,int channel,long * value) xe_hwmon_get_voltage() argument
795 xe_hwmon_temp_is_visible(struct xe_hwmon * hwmon,u32 attr,int channel) xe_hwmon_temp_is_visible() argument
807 xe_hwmon_temp_read(struct xe_hwmon * hwmon,u32 attr,int channel,long * val) xe_hwmon_temp_read() argument
825 xe_hwmon_power_is_visible(struct xe_hwmon * hwmon,u32 attr,int channel) xe_hwmon_power_is_visible() argument
890 xe_hwmon_power_read(struct xe_hwmon * hwmon,u32 attr,int channel,long * val) xe_hwmon_power_read() argument
908 xe_hwmon_power_write(struct xe_hwmon * hwmon,u32 attr,int channel,long val) xe_hwmon_power_write() argument
922 xe_hwmon_curr_is_visible(const struct xe_hwmon * hwmon,u32 attr,int channel) xe_hwmon_curr_is_visible() argument
945 xe_hwmon_curr_read(struct xe_hwmon * hwmon,u32 attr,int channel,long * val) xe_hwmon_curr_read() argument
956 xe_hwmon_curr_write(struct xe_hwmon * hwmon,u32 attr,int channel,long val) xe_hwmon_curr_write() argument
967 xe_hwmon_in_is_visible(struct xe_hwmon * hwmon,u32 attr,int channel) xe_hwmon_in_is_visible() argument
980 xe_hwmon_in_read(struct xe_hwmon * hwmon,u32 attr,int channel,long * val) xe_hwmon_in_read() argument
992 xe_hwmon_energy_is_visible(struct xe_hwmon * hwmon,u32 attr,int channel) xe_hwmon_energy_is_visible() argument
1012 xe_hwmon_energy_read(struct xe_hwmon * hwmon,u32 attr,int channel,long * val) xe_hwmon_energy_read() argument
1024 xe_hwmon_fan_is_visible(struct xe_hwmon * hwmon,u32 attr,int channel) xe_hwmon_fan_is_visible() argument
1043 xe_hwmon_fan_input_read(struct xe_hwmon * hwmon,int channel,long * val) xe_hwmon_fan_input_read() argument
1082 xe_hwmon_fan_read(struct xe_hwmon * hwmon,u32 attr,int channel,long * val) xe_hwmon_fan_read() argument
1094 xe_hwmon_is_visible(const void * drvdata,enum hwmon_sensor_types type,u32 attr,int channel) xe_hwmon_is_visible() argument
1132 xe_hwmon_read(struct device * dev,enum hwmon_sensor_types type,u32 attr,int channel,long * val) xe_hwmon_read() argument
1170 xe_hwmon_write(struct device * dev,enum hwmon_sensor_types type,u32 attr,int channel,long val) xe_hwmon_write() argument
1196 xe_hwmon_read_label(struct device * dev,enum hwmon_sensor_types type,u32 attr,int channel,const char ** str) xe_hwmon_read_label() argument
1237 int channel; xe_hwmon_get_preregistration_info() local
[all...]
/linux/drivers/hv/
H A Dchannel_mgmt.c29 static void init_vp_index(struct vmbus_channel *channel);
46 /* Fibre Channel */
170 * The rescinded channel may be blocked waiting for a response from the host;
173 static void vmbus_rescind_cleanup(struct vmbus_channel *channel) in vmbus_rescind_cleanup() argument
180 channel->rescind = true; in vmbus_rescind_cleanup()
184 if (msginfo->waiting_channel == channel) { in vmbus_rescind_cleanup()
202 static u16 hv_get_dev_type(const struct vmbus_channel *channel) in hv_get_dev_type() argument
204 const guid_t *guid = &channel->offermsg.offer.if_type; in hv_get_dev_type()
207 if (is_hvsock_channel(channel) || is_unsupported_vmbus_devs(guid)) in hv_get_dev_type()
221 * @buf: Raw buffer channel data
[all …]
/linux/drivers/tty/serial/jsm/
H A Djsm_tty.c66 struct jsm_channel *channel = in jsm_tty_get_mctrl() local
69 jsm_dbg(IOCTL, &channel->ch_bd->pci_dev, "start\n"); in jsm_tty_get_mctrl()
71 result = jsm_get_mstat(channel); in jsm_tty_get_mctrl()
76 jsm_dbg(IOCTL, &channel->ch_bd->pci_dev, "finish\n"); in jsm_tty_get_mctrl()
88 struct jsm_channel *channel = in jsm_tty_set_mctrl() local
91 jsm_dbg(IOCTL, &channel->ch_bd->pci_dev, "start\n"); in jsm_tty_set_mctrl()
94 channel->ch_mostat |= UART_MCR_RTS; in jsm_tty_set_mctrl()
96 channel->ch_mostat &= ~UART_MCR_RTS; in jsm_tty_set_mctrl()
99 channel->ch_mostat |= UART_MCR_DTR; in jsm_tty_set_mctrl()
101 channel->ch_mostat &= ~UART_MCR_DTR; in jsm_tty_set_mctrl()
[all …]
/linux/drivers/usb/musb/
H A Dmusbhsdma.c54 struct dma_channel channel; member
66 struct musb_dma_channel channel[MUSB_HSDMA_CHANNELS]; member
74 static void dma_channel_release(struct dma_channel *channel);
79 struct dma_channel *channel; in dma_controller_stop() local
84 "Stopping DMA controller while channel active\n"); in dma_controller_stop()
88 channel = &controller->channel[bit].channel; in dma_controller_stop()
89 dma_channel_release(channel); in dma_controller_stop()
104 struct dma_channel *channel = NULL; in dma_channel_allocate() local
110 musb_channel = &(controller->channel[bit]); in dma_channel_allocate()
115 channel = &(musb_channel->channel); in dma_channel_allocate()
[all …]

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