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/freebsd/sys/contrib/device-tree/Bindings/iio/adc/
H A Dti,am3359-adc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/ti,am3359-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Miquel Raynal <miquel.raynal@bootlin.com>
15 - enum:
16 - ti,am3359-adc
17 - ti,am4372-adc
18 - items:
19 - enum:
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/freebsd/sys/contrib/device-tree/Bindings/input/touchscreen/
H A Dti-tsc-adc.txt1 * TI - TSC ADC (Touschscreen and analog digital converter)
5 - mfd
7 "ti,am3359-tscadc" for AM335x/AM437x SoCs
8 "ti,am654-tscadc", "ti,am3359-tscadc" for AM654 SoCs
9 - child "tsc"
10 compatible: Should be "ti,am3359-tsc".
13 ti,x-plate-resistance: X plate resistance
14 ti,coordinate-readouts: The sequencer supports a total of 16
15 programmable steps each step is used to
23 ti,wire-config: Different boards could have a different order for
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/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Dam335x-pocketbeagle.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
7 /dts-v1/;
10 #include "am335x-osd335x-common.dtsi"
11 #include <dt-bindings/leds/common.h>
15 compatible = "ti,am335x-pocketbeagle", "ti,am335x-bon
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/freebsd/sys/contrib/dev/rtw89/
H A Dcore.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2019-2020 Realtek Corporation
54 #define RTW89_RSSI_RAW_TO_DBM(rssi) ((s8)((rssi) >> RSSI_FACTOR) - MAX_RSSI)
111 RTW89_CH_6G_BAND_IDX6, /* Ultra-high */
112 RTW89_CH_6G_BAND_IDX7, /* Ultra-high */
271 * RTW89_ADDR_CAM_SEC_ALL_UNI : 0 - 6 unicast
272 * RTW89_ADDR_CAM_SEC_NORMAL : 0 - 1 unicast, 2 - 4 group, 5 - 6 BIP
273 * RTW89_ADDR_CAM_SEC_4GROUP : 0 - 1 unicast, 2 - 5 group, 6 BIP
771 #define RTW89_MIN_VALID_POWER_CONSTRAINT (-10) /* unit: dBm */
977 /* The follow-up are derived from the above. We must ensure that it
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H A Dphy.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2019-2020 Realtek Corporation
6 #include "chan.h"
20 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; in rtw89_phy0_phy1_offset()
22 return phy->phy0_phy1_offset(rtwdev, addr); in rtw89_phy0_phy1_offset()
28 u32 bit_rate = report->bit_rate; in get_max_amsdu_len()
35 if (report->might_fallback_legacy) in get_max_amsdu_len()
50 return rtwdev->chip->max_amsdu_limit; in get_max_amsdu_len()
66 ra_mask |= GENMASK_ULL(highest_mcs - gap, 0) << nss; in get_mcs_ra_mask()
69 ra_mask |= GENMASK_ULL(highest_mcs - gap * 2, 0) << nss; in get_mcs_ra_mask()
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/freebsd/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dar9300_reset.c70 static inline void ar9300_set_rf_mode(struct ath_hal *ah, struct ieee80211_channel *chan);
71 static inline HAL_BOOL ar9300_init_cal(struct ath_hal *ah, struct ieee80211_channel *chan, HAL_BOOL…
121 ahp->ah_hwp = HAL_TRUE_CHIP; in ar9300_attach_hw_platform()
131 ar9300_set_ifs_timing(struct ath_hal *ah, struct ieee80211_channel *chan) in ar9300_set_ifs_timing() argument
137 if (IEEE80211_IS_CHAN_HALF(chan)) { /* half rates */ in ar9300_set_ifs_timing()
140 if (IS_5GHZ_FAST_CLOCK_EN(ah, chan)) { /* fast clock */ in ar9300_set_ifs_timing()
152 if (IS_5GHZ_FAST_CLOCK_EN(ah, chan)) { /* fast clock */ in ar9300_set_ifs_timing()
196 * Mask used to construct AAD for CCMP-AES in ar9300_init_mfp()
197 * Cisco spec defined bits 0-3 as mask in ar9300_init_mfp()
218 ar9300_get_channel_centers(struct ath_hal *ah, const struct ieee80211_channel *chan, in ar9300_get_channel_centers() argument
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/freebsd/share/misc/
H A Dpci_vendors5 # Date: 2025-10-18 03:15:01
8 # the PCI ID Project at https://pci-ids.ucw.cz/.
14 # (version 2 or higher) or the 3-clause BSD License.
25 # device device_name <-- single tab
26 # subvendor subdevice subsystem_name <-- two tabs
30 # This is a relabelled RTL-8139
31 8139 AT-2500TX V3 Ethernet
41 7a09 PCI-to-PCI Bridge
51 7a19 PCI-to-PCI Bridge
57 7a29 PCI-to-PCI Bridge
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