Home
last modified time | relevance | path

Searched full:ccipll (Results 1 – 8 of 8) sorted by relevance

/linux/Documentation/devicetree/bindings/clock/
H A Dmediatek,mt8196-sys-clock.yaml21 The apmixedsys, apmixedsys_gp2, vlpckgen, armpll, ccipll, mfgpll and ptppll
35 - mediatek,mt8196-ccipll-pll-ctrl
/linux/drivers/clk/mediatek/
H A Dclk-mt8196-mcu.c87 PLL(CLK_CCIPLL, "ccipll", CCIPLL_CON0, CCIPLL_CON0, 0, 0, PLL_AO,
103 { .compatible = "mediatek,mt8196-ccipll-pll-ctrl", .data = &cci_plls },
H A Dclk-mt8186-apmixedsys.c48 * armpll_ll/armpll_bl/ccipll are main clock source of AP MCU,
55 PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x0224, 0x0230, 0,
H A Dclk-mt8186-mcu.c28 "ccipll",
H A Dclk-mt8183-apmixedsys.c117 PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x0290, 0x029C, 0,
H A Dclk-mt6765.c709 PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x022C, 0x0238, 0,
754 /* MPLL, CCIPLL, MAINPLL set HW mode, TDCLKSQ, CLKSQ1 */ in clk_mt6765_apmixed_probe()
H A Dclk-mt8183.c604 "ccipll",
H A Dclk-mt6779.c1188 PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x02A0, 0x02AC, 0,