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/linux/arch/riscv/boot/dts/sophgo/
H A Dsg2044-cpus.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 #address-cells = <2>;
8 #size-cells = <2>;
11 #address-cells = <1>;
12 #size-cells = <0>;
13 timebase-frequency = <50000000>;
18 i-cache-block-size = <64>;
19 i-cache-size = <65536>;
20 i-cache-sets = <512>;
21 d-cache-block-size = <64>;
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/linux/arch/riscv/boot/dts/spacemit/
H A Dk1.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
6 #include <dt-bindings/clock/spacemit,k1-syscon.h>
8 /dts-v1/;
10 #address-cells = <2>;
11 #size-cells = <2>;
16 #address-cells = <1>;
17 #size-cells = <0>;
18 timebase-frequency = <24000000>;
20 cpu-map {
57 riscv,isa-base = "rv64i";
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/linux/arch/riscv/mm/
H A Dcacheflush.c1 // SPDX-License-Identifier: GPL-2.0-only
30 * the IPI. The RISC-V spec states that a hart must execute a data fence in flush_icache_all()
34 * IPIs on RISC-V are triggered by MMIO writes to either CLINT or in flush_icache_all()
35 * S-IMSIC, so the fence ensures previous data writes "happen before" in flush_icache_all()
48 * Performs an icache flush for the given MM context. RISC-V has no direct
52 * single-hart processes on a many-hart machine, ie 'make -j') we avoid the
65 mask = &mm->context.icache_stale_mask; in flush_icache_mm()
78 if (mm == current->active_mm && local) { in flush_icache_mm()
104 if (!test_bit(PG_dcache_clean, &folio->flags)) { in flush_icache_pte()
106 set_bit(PG_dcache_clean, &folio->flags); in flush_icache_pte()
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/linux/Documentation/devicetree/bindings/riscv/
H A Dcpus.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V CPUs
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 This document uses some terminology common to the RISC-V community
19 mandated by the RISC-V ISA: a PC and some registers. This
27 - $ref: /schemas/cpu.yaml#
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/linux/arch/riscv/kernel/
H A Dcpufeature.c1 // SPDX-License-Identifier: GPL-2.0-only
24 #include <asm/text-patching.h>
32 #define NUM_ALPHA_EXTS ('z' - 'a' + 1)
43 /* Per-cpu ISA extensions. */
49 * riscv_isa_extension_base() - Get base extension word
63 * __riscv_isa_extension_available() - Check whether given extension
89 return -EPROBE_DEFER; in riscv_ext_f_depends()
96 pr_err("Zicbom detected in ISA string, disabling as no cbom-block-size found\n"); in riscv_ext_zicbom_validate()
97 return -EINVAL; in riscv_ext_zicbom_validate()
100 pr_err("Zicbom disabled as cbom-block-size present, but is not a power-of-2\n"); in riscv_ext_zicbom_validate()
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/linux/include/acpi/
H A Dactbl2.h1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */
4 * Name: actbl2.h - ACPI Table Definitions
6 * Copyright (C) 2000 - 2025, Intel Corp.
54 #define ACPI_SIG_RHCT "RHCT" /* RISC-V Hart Capabilities Table */
55 #define ACPI_SIG_RIMT "RIMT" /* RISC-V IO Mapping Table */
63 * All tables must be byte-packed to match the ACPI specification, since
73 * essentially useless for dealing with packed data in on-disk formats or
82 * AEST - Arm Error Source Table
93 /* Common Subtable header - one per Node Structure (Subtable) */
326 * AGDI - Arm Generic Diagnostic Dump and Reset Device Interface
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