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/linux/net/mac80211/
H A DKconfig136 Selecting this option causes mac80211 to print out
147 Selecting this option causes mac80211 to print out
158 Selecting this option causes mac80211 to print out
179 Selecting this option causes mac80211 to print out
190 Selecting this option causes mac80211 to print out
201 Selecting this option causes mac80211 to print out very
214 Selecting this option causes mac80211 to print out very
227 Selecting this option causes mac80211 to print out very
240 Selecting this option causes mac80211 to print out very
253 Selecting this option causes mac80211 to print out very verbose mesh
[all …]
/linux/Documentation/ABI/testing/
H A Ddebugfs-scmi-raw11 Each write to the entry causes one command request to be built
29 Each write to the entry causes one command request to be built
45 Each write to the entry causes one command request to be built
65 Each write to the entry causes one command request to be built
97 causes the internal queues of any kind of received message,
116 Each write to the entry causes one command request to be built
143 Each write to the entry causes one command request to be built
169 Each write to the entry causes one command request to be built
198 Each write to the entry causes one command request to be built
H A Dsysfs-bus-iio-light-tsl27725 Causes an internal calibration of the als gain trim
12 Causes a recalculation and adjustment to the
/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a76/
H A Dcache.json11 …event counts any load or store operation or page table walk access which causes data to be read fr…
15 …. In particular, any access which could count the L1D_CACHE_REFILL event causes this event to coun…
35 … cache refill. This event counts any cacheable transaction from L1 which causes data to be read fr…
81 … "PublicDescription": "This event counts on any data access which causes L2D_TLB_REFILL to count.",
85 …"PublicDescription": "This event counts on any instruction access which causes L2D_TLB_REFILL to c…
/linux/tools/perf/pmu-events/arch/x86/ivytown/
H A Duncore-power.json151 …te. In other words, a wake event occurred before the timer expired that causes a transition into …
160 …te. In other words, a wake event occurred before the timer expired that causes a transition into …
169 …te. In other words, a wake event occurred before the timer expired that causes a transition into …
178 …te. In other words, a wake event occurred before the timer expired that causes a transition into …
187 …te. In other words, a wake event occurred before the timer expired that causes a transition into …
196 …te. In other words, a wake event occurred before the timer expired that causes a transition into …
205 …te. In other words, a wake event occurred before the timer expired that causes a transition into …
214 …te. In other words, a wake event occurred before the timer expired that causes a transition into …
223 …te. In other words, a wake event occurred before the timer expired that causes a transition into …
232 …te. In other words, a wake event occurred before the timer expired that causes a transition into …
[all …]
H A Dvirtual-memory.json3 …ion": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that c…
27 …ion": "Demand load Miss in all translation lookaside buffer (TLB) levels causes an page walk of an…
45 …ion": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that c…
67 … "PublicDescription": "Miss in all TLB levels causes a page walk of any page size (4K/2M/4M/1G).",
85 …"PublicDescription": "Miss in all TLB levels causes a page walk that completes of any page size (4…
/linux/tools/perf/pmu-events/arch/x86/haswell/
H A Dvirtual-memory.json48 …ion": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that c…
57 "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)",
65 …ion": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that c…
74 …ion": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that c…
96 … "PublicDescription": "Miss in all TLB levels causes a page walk of any page size (4K/2M/4M/1G).",
163 "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (4K)",
202 "PublicDescription": "Misses in ITLB that causes a page walk of any page size.",
243 "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (1G)",
251 … "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",
260 "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
/linux/tools/perf/pmu-events/arch/x86/haswellx/
H A Dvirtual-memory.json48 …ion": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that c…
57 "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)",
65 …ion": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that c…
74 …ion": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that c…
96 … "PublicDescription": "Miss in all TLB levels causes a page walk of any page size (4K/2M/4M/1G).",
163 "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (4K)",
202 "PublicDescription": "Misses in ITLB that causes a page walk of any page size.",
243 "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (1G)",
251 … "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",
260 "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
/linux/tools/perf/pmu-events/arch/x86/broadwellx/
H A Dvirtual-memory.json37 …ion": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that c…
46 "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)",
56 …ion": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that c…
66 …ion": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that c…
149 "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (4K)",
230 "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (1G)",
240 … "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",
250 "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
/linux/tools/perf/pmu-events/arch/x86/broadwellde/
H A Dvirtual-memory.json37 …ion": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that c…
46 "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)",
56 …ion": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that c…
66 …ion": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that c…
149 "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (4K)",
230 "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (1G)",
240 … "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",
250 "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
/linux/tools/perf/pmu-events/arch/x86/broadwell/
H A Dvirtual-memory.json37 …ion": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that c…
46 "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)",
56 …ion": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that c…
66 …ion": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that c…
149 "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (4K)",
230 "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (1G)",
240 … "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",
250 "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
/linux/tools/perf/pmu-events/arch/x86/ivybridge/
H A Dvirtual-memory.json11 …ion": "Demand load Miss in all translation lookaside buffer (TLB) levels causes an page walk of an…
29 …ion": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that c…
51 … "PublicDescription": "Miss in all TLB levels causes a page walk of any page size (4K/2M/4M/1G).",
69 …"PublicDescription": "Miss in all TLB levels causes a page walk that completes of any page size (4…
/linux/tools/perf/pmu-events/arch/x86/rocketlake/
H A Dvirtual-memory.json22 "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)",
86 "BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)",
150 "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)",
159 "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",
168 "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
/linux/tools/perf/pmu-events/arch/x86/tigerlake/
H A Dvirtual-memory.json22 "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)",
86 "BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)",
150 "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)",
159 "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",
168 "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
/linux/tools/perf/pmu-events/arch/x86/icelake/
H A Dvirtual-memory.json22 "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)",
86 "BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)",
150 "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)",
159 "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",
168 "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
/linux/tools/perf/pmu-events/arch/x86/lunarlake/
H A Dvirtual-memory.json79 "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)",
218 "BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)",
366 "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)",
386 "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",
406 "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
/linux/Documentation/input/devices/
H A Datarikbd.rst206 DISABLE) then causes port 0 to again be scanned as if it were a mouse, and
227 Any byte following an 0x80 command byte other than 0x01 is ignored (and causes
233 The RESET command or function causes the ikbd to perform a simple self-test.
248 ; mss=0xy, mouse button press or release causes mouse
250 ; where y=1, mouse key press causes absolute report
251 ; and x=1, mouse key release causes absolute report
383 mouse motion. This causes mouse motion toward the user to be negative in sign
395 This causes mouse motion toward the user to be positive in sign and away from
406 its output has been paused also causes an implicit RESUME this command can be
440 causes any accumulated motion to be immediately queued as packets, if the
[all …]
/linux/tools/perf/pmu-events/arch/x86/skylake/
H A Dvirtual-memory.json31 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size…
104 …"BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page s…
194 …"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page size…
203 "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (1G)",
212 … "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",
221 "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
/linux/tools/perf/pmu-events/arch/x86/skylakex/
H A Dvirtual-memory.json31 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size…
104 …"BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page s…
194 …"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page size…
203 "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (1G)",
212 … "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",
221 "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
/linux/tools/perf/pmu-events/arch/x86/cascadelakex/
H A Dvirtual-memory.json31 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size…
104 …"BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page s…
194 …"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page size…
203 "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (1G)",
212 … "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",
221 "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
/linux/tools/perf/pmu-events/arch/x86/icelakex/
H A Dvirtual-memory.json22 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size…
86 …"BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page s…
150 …"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page size…
159 … "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",
168 "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
/linux/Documentation/arch/powerpc/
H A Deeh-pci-error-recovery.rst34 Causes of EEH Errors
43 The most common software bug, is one that causes the device to
49 years. Other possible causes of EEH errors include data or
178 This last call causes the device driver for the card to be stopped,
179 which causes uevents to go out to user space. This triggers
306 - A minor complaint is that resetting the network card causes
312 causes havoc to mounted file systems. Scripts cannot post-facto
/linux/drivers/bluetooth/
H A Dbtintel_pcie.h93 /* Causes for the FH register interrupts */
99 /* Causes for the HW register interrupts */
135 /* causes for the MBOX interrupts */
440 * @def_irq: default irq for all causes
441 * @fh_init_mask: initial unmasked rxq causes
442 * @hw_init_mask: initial unmaksed hw causes
/linux/drivers/net/ethernet/freescale/dpaa2/
H A Ddprtc.c85 * Each interrupt can have up to 32 causes. The enable/disable control's the
86 * overall interrupt state. if the interrupt is disabled no causes will cause
158 * Every interrupt can have up to 32 causes and the interrupt model supports
190 * Every interrupt can have up to 32 causes and the interrupt model supports
/linux/Documentation/driver-api/
H A Dreset.rst88 That is, an assert causes the reset line to be asserted immediately, and a
89 deassert causes the reset line to be deasserted immediately.
116 shared, but for those only the first trigger request causes an actual pulse to
143 Passing a NULL pointer to the reset_control functions causes them to return

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